Implementation Aspects of Multi-Level Frame Preemption in TSN

Knezic, Mladen; Kovacevic, Milos; Ivanovic, Zeljko

doi:10.1109/etfa46521.2020.9211914

Cited by 5 publications

(2 citation statements)

References 7 publications

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“…Here, the authors also compare TAS and frame preemption from a qualitative standpoint and promote the multi-level frame preemption feature as a viable alternative to TAS. Furthermore, Knezic et al [27] provided an enhanced implementation approach for the multi-level preemption feature and the formal worstcase traversal time analysis of this approach was provided by Ojewale et al [26]. On another front, a work by Nasrallah et al [10] conducts a performance comparison of TAS and Asynchronous Traffic Shaping (ATS).…”

Section: Related Workmentioning

confidence: 99%

Implementation Cost Comparison of TSN Traffic Control Mechanisms

Pruski¹,

Yomsi²,

Berger³

et al. 2021

2021 26th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA )

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The IEEE Time-Sensitive Networking (TSN) Task Group specifies a set of standards that enables real-time communication with predictable and bounded delays over the Ethernet. Specifically, TSN introduces a new set of so-called shapers, which regulate traffic arrival and transmission in the networks. Prominent among those are the IEEE 802.1 Qbv Time Aware Shaper (TAS) and IEEE 802.1Qav Credit-Based Shaper (CBS).Another traffic control mechanism is the IEEE 802.1Qbu Frame Preemption. Most works in the literature have focused on the quantitative performance comparison between these mechanisms. However, the discussion on how they compare in terms of implementation cost has received less attention. In this paper,we provide a comprehensive comparison of the implementation cost of the aforementioned TSN traffic control mechanisms. This comparison can help system designers in choosing which of the mechanism(s) to deploy for their applications

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Section: Related Workmentioning

confidence: 99%

Implementation Cost Comparison of TSN Traffic Control Mechanisms

Pruski¹,

Yomsi²,

Berger³

et al. 2021

2021 26th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA )

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“…Service-oriented dynamic connection management for software-defined internet of vehicles [26] A distributed in-vehicle service architecture using dynamically created web Services [27] SODA: Service-Oriented Architecture for Runtime Adaptive Driver Assistance Systems [28] RACE: A centralized platform computer based architecture for automotive applications [29] Achieving determinism in adaptive AUTOSAR [30] Software-Defined Networking in Automotive [31] Figure Analysis and modeling of asynchronous traffic shaping in time sensitive networks [40] Formal worst-case timing analysis of ethernet tsn's time-aware and peristaltic shapers [41] On the Performance of Stream-based, Class-based Time-aware Shaping and Frame Preemption in TSN [42] Gate-Shrunk Time Aware Shaper: Low-Latency Converged Network for 5G Fronthaul and M2M Services [43] An Approach to Improve Bandwidth Utilization in TSN Networks [44] Time-Triggered Switch-Memory-Switch Architecture for Time-Sensitive Networking Switches [45] SP-PIFO: Approximating Push-In First-Out Behaviors using Strict-Priority Queues [46] Chamaleon: Predictable Latency and high Utilization with Queue-Aware and Adaptive Source Routing [47] Performance assessment of the IEEE802.1Qch in an automotive scenario [48] Assessments of Real-Time Communications over TSN Automotive Networks [49] No-wait packet scheduling for IEEE time-sensitive networks (TSN) [50] Development of an Ethernet-based heuristic time-sensitive networking scheduling algorithm for real-time in-vehicle data transmission [51] Deadline-aware online scheduling of TSN flows for automotive applications [52] Implementation Aspects of Multi-Level Frame Preemption in TSN [53] A novel frame preemption model in TSN networks [54] Quantitative performance comparison of various traffic shapers in time-sensitive networking [55] Comparison of IEEE802.1Q and IEEE802.1AVB in multi switch environment in embedded system [56] Insights on the Performance and Configuration of AVB and TSN in Automotive Ethernet Networks [20] An Architecture for In-Vehicle Networks [16] Figure Survey and taxonomy of information-centric vehicular networking security attacks [83] ...…”

Section: Software Defined Vehiclementioning

confidence: 99%

Contributions to the design, development and evaluation of network processors for automotive zonal gateway controllers

González Mariño

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(English) This PhD dissertation analyzes the evolution of vehicular networks and focuses on the main network processing platform integrated in them: the Gateway (GW). First, a thorough analysis of state of the art technologies involved in vehicular networks is performed, leading to the definition of the requirements of future network processing platforms. Then, the available options in the state of the art for network processing, both in industry and academia, are analyzed. This analysis shows a gap in this area: there is currently no architecture fulfilling all the requirements of future automotive GW controllers. Moreover, Hardware (HW) accelerators and custom processor design are identified as a key differentiation factor which boosts the performance of the devices. Linking the result of this analysis with the current trend towards application specific processors, this thesis proposes the novel Elastic Gateway (eGW) System on Chip (SoC) architecture as a high performance network processor for future zonal GW controllers. The proposed architecture aims at fulfilling the identified gap, advancing towards future GW SoC solutions. Elastic Gateway SoC concept aims at synthesizing a scalable and future-proof architecture embracing all new and already established functions and features demanded in a zonal gateway controller for the new era of mobility. The challenge now is not only to design the right processor that can meet the requirements available today, but also to make this design suitable for the future. For this reason, the modularity, flexibility, scalability and configurability of these future processors take, more than ever, a starring role in the early design stages. This thesis is also providing a complete lifecycle methodology for the design and validation of different network processing products based on the proposed eGW SoC architecture. Throughout this work the architecture is evaluated from a functional perspective, proving how the differefnt technologies required in future vehicular networks are integrated in eGW and how the previously defined requirements are met. Then, a proof of concept is implemented showing the viability of the proposed concept and methodology, providing details of the experimental results. The architecture is also evaluated from a scalability point of view, looking at HW cost and power consumption, proving that eGW is able to provide a high level of performance at a reasonable cost. Together, the eGW SoC concept and methodology become an alternative that can contribute to overcome the existing challenges, advancing over state of the art solutions. (Català) Aquesta tesi doctoral analitza l'evolució de les xarxes vehiculars i se centra en la principal plataforma de processament de xarxa integrada: el Gateway (GW). Primer es realitza una anàlisi exhaustiva de les tecnologies capdavanteres involucrades en les xarxes vehiculars, que porta a la definició dels requisits de les futures plataformes de processament de xarxes. Després, s'analitzen les opcions disponibles a l'estat de l'art per al processament de xarxes, tant a la indústria com al món acadèmic. Aquesta anàlisi mostra una bretxa en aquesta àrea: actualment no hi ha cap arquitectura que compleixi amb tots els requisits dels futurs controladors GW per a automòbils. A més, els acceleradors de hardware (HW) i el disseny de processadors dedicats s'identifiquen com un factor de diferenciació clau que augmenta el rendiment dels dispositius. Vinculant el resultat d'aquesta anàlisi amb la tendència actual cap als processadors d'aplicació específica, aquesta tesi proposa una nova arquitectura anomenada Elastic Gateway (eGW) System on Chip (SoC) com a processador de xarxes d'alt rendiment per als futurs controladors GW. L'arquitectura proposada té com a objectiu cobrir la bretxa identificada i avançar cap a futures solucions GW SoC. El concepte Elastic Gateway SoC té com a objectiu sintetitzar una arquitectura escalable i preparada per al futur que inclogui totes les funcions i característiques noves i ja establertes que s'exigeixen en un controlador \textit{gateway} per a la nova era de la mobilitat. El desafiament ara no és només dissenyar el processador correcte que pugui complir amb els requisits disponibles actualment, sinó també fer que aquest disseny sigui adequat per al futur. Per això, la modularitat, la flexibilitat, l'escalabilitat i la configurabilitat d'aquests futurs processadors cobren, més que mai, un paper protagonista en les primeres etapes de disseny. Aquesta tesi també proporciona una metodologia de cicle de vida completa per al disseny i la validació de diferents productes de processament de xarxa basats en larquitectura proposada de eGW SoC. Al llarg d'aquest treball s'avalua l'arquitectura des d'una perspectiva funcional, demostrant com s'integren a eGW les diferents tecnologies requerides en xarxes vehiculars futures i com es compleixen els requisits definits anteriorment. Per tant, s'implementa una prova de concepte que mostra la viabilitat del concepte i la metodologia proposada, proporcionant detalls dels resultats experimentals. L'arquitectura també s'avalua des del punt de vista de l'escalabilitat, considerant el cost de recursos HW i el consum d'energia, demostrant que eGW pot proporcionar un nivell alt de rendiment a un cost raonable. Tot plegat, el concepte i la metodologia d'eGW SoC proposen una alternativa que pot contribuir a superar els desafiaments existents, avançant sobre l'estat de l'art. (Español) Esta tesis doctoral analiza la evolución de las redes vehiculares y se centra en la principal plataforma de procesamiento de red integrada en ellas: el Gateway (GW). Primero se realiza un análisis exhaustivo de las tecnologías punteras involucradas en las redes vehiculares, que lleva a la definición de los requisitos de las futuras plataformas de procesamiento de redes. A continuación, se analizan las opciones disponibles en el estado del arte para el procesamiento de redes, tanto en la industria como en el mundo académico. Este análisis muestra una brecha en esta área: actualmente no existe ninguna arquitectura que cumpla con todos los requisitos de los futuros controladores GW para automóviles. Además, los aceleradores de hardware (HW) y el diseño de procesadores dedicados se identifican como un factor de diferenciación clave que aumenta el rendimiento de los dispositivos. Vinculando el resultado de este análisis con la tendencia actual hacia los procesadores de aplicación específica, esta tesis propone la nueva arquitectura Elastic Gateway (eGW) System on Chip (SoC) como un procesador de redes de alto rendimiento para los futuros controladores GW. La arquitectura propuesta tiene como objetivo cubrir la brecha identificada, avanzando hacia futuras soluciones GW SoC. El concepto Elastic Gateway SoC tiene como objetivo sintetizar una arquitectura escalable y preparada para el futuro que abarque todas las funciones y características nuevas y ya establecidas que se exigen en un controlador gateway para la nueva era de la movilidad. El desafío ahora no es solo diseñar el procesador correcto que pueda cumplir con los requisitos disponibles en la actualidad, sino también hacer que este diseño sea adecuado para el futuro. Por ello, la modularidad, flexibilidad, escalabilidad y configurabilidad de estos futuros procesadores cobran, más que nunca, un papel protagonista en las primeras etapas de diseño. Esta tesis también proporciona una metodología de ciclo de vida completa para el diseño y la validación de diferentes productos de procesamiento de red basados en la arquitectura propuesta de eGW SoC. A lo largo de este trabajo se evalúa la arquitectura desde una perspectiva funcional, demostrando cómo se integran en eGW las diferentes tecnologías requeridas en futuras redes vehiculares y cómo se cumplen los requisitos definidos anteriormente. Después, se implementa una prueba de concepto que muestra la viabilidad del concepto y la metodología propuesta, proporcionando detalles de los resultados experimentales. La arquitectura también se evalúa desde el punto de vista de la escalabilidad, considerando el coste de recursos HW y el consumo de energía, demostrando que eGW puede proporcionar un alto nivel de rendimiento a un coste razonable. En conjunto, el concepto y la metodología de eGW SoC proponen una alternativa que puede contribuir a superar los desafíos existentes, avanzando sobre el estado del arte.

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Worst-case traversal time analysis of TSN with multi-level preemption

Yomsi

Nikolic

2021

Journal of Systems Architecture

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Implementation Aspects of Multi-Level Frame Preemption in TSN

Cited by 5 publications

References 7 publications

Implementation Cost Comparison of TSN Traffic Control Mechanisms

Implementation Cost Comparison of TSN Traffic Control Mechanisms

Contributions to the design, development and evaluation of network processors for automotive zonal gateway controllers

Worst-case traversal time analysis of TSN with multi-level preemption

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