Implementation and Verification of IEEE-754 64-bit Floating-Point Arithmetic Library for 8-bit Soft-Core Processors

Ali, Ehsan; Pora, Wanchalerm

doi:10.1109/ieecon48109.2020.229455

Cited by 5 publications

(4 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The results of those methods were obtained and then compared by running the code on both cores. The IEEE-754 64-bit floating point arithmetic library [77], which has relatively high complexity, was used to expose potential faults. The library has numerous bitwise operations that boost the chance of discovering processor bugs, even if a single bit is miscalculated as it tries to compute 64-bit floating point numbers on an 8-bit processor.…”

Section: Math Library Executionmentioning

confidence: 99%

A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture

Ali

Pora

2022

Electronics

View full text Add to dashboard Cite

This paper proposes a new deterministic branch prediction unit to achieve a uniformly timed instruction set architecture (ISA). The deterministic ISA is achieved by utilizing two address buses in conjunction with dual-port block RAMs that are common in commercial FPGAs. The goal is to remove mandatory branch and load delays to achieve a uniform one clock cycle per every instruction. To demonstrate the concept, the proposed architecture is applied to the Xilinx PicoBlaze firm core. The result is a new soft core named DAP-Zipi8 that reduces the clock per instruction (CPI) metric of PicoBlaze from two to one at the expense of extra logic and a longer critical path. The increased critical path reduces maximum achievable clock speed from 357.509 MHz to 224.022 MHz. Merging the gain in CPI with the loss in maximum clock frequency still improves overall processor performance by 18.28–19.49%. The high-performance deterministic DAP-Zipi8 is a viable choice for hard RTES applications.

show abstract

Section: Math Library Executionmentioning

confidence: 99%

A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture

Ali

Pora

2022

Electronics

View full text Add to dashboard Cite

show abstract

“…A testbench which puts PicoBlaze and PauloBlaze alongside of two block RAMs holding exact copy of a test program was implemented. A test program with several calls to routines of an IEEE 754 floating point library (Ali and Pora, 2020) was executed. The clock accuracy comparison was skipped, and only the final calculation results were recorded and then compared.…”

Section: Related Workmentioning

confidence: 99%

Modular transformation of embedded systems from firm-cores to soft-cores

Ali¹,

Pora²

2021

IJES

Self Cite

View full text Add to dashboard Cite

Although there are many 8-bit IP processor cores available, only a few, such as Xilinx PicoBlaze and Lattice Mico8 firm-cores are reliable enough to be used in commercial products. One of the drawbacks is that their codes are confined to vendor-specific primitives. It is inefficient to implement a PicoBlaze processor on non-Xilinx FPGA devices. In this paper we propose a systematic approach that transforms primitive-level designs (firm-cores) to vendor independent designs (soft-cores), while modularising them during the process. This makes modification and implementation of designs on any FPGA devices possible. To demonstrate the idea, our soft-core version of PicoBlaze is implemented on a Lattice iCE40LP1k FPGA device and is shown to be fully compatible with the original PicoBlaze macro. Rigorous verification mechanisms have been employed to ensure the validity of the porting process; therefore, the quality of transformation matches the industry expectation.

show abstract

“…Take implementing a 64-bit floating point library (very complex algorithm) on PicoBlaze as an example [165]. After writing the routines that perform floating point operations in assembly language of PicoBlaze we can verify the result by first writing the PicoBlaze floating point arithmetic result into the "Shared BRAM" and then compare the result with of those produced by ARM processor (either by a software library or hardware floating point unit).…”

Section: Proposed Development Cyclementioning

confidence: 99%

“…To verify conditional jumps, call, return, and stack mechanism, both cores execute a sequence of complicated instructions, then the results are compared. We exploit the IEEE754 64-bit Floating-Point Arithmetic Library for 8-bit Soft-Core Processors [165] which has enough complexity to expose bugs, if any. The library uses 8-bit registers and scratch pad memory to perform 64-bit normal/subnormal floating point (FP) operations.…”

Section: Isolated Instruction Executionmentioning

confidence: 99%

A morphable FPGA soft processor using LLVM infrastructure targeting low-power application-specific embedded systems

Ali¹

View full text Add to dashboard Cite

The reconfigurable computing (RC) aims to combine the flexibility of General-Purpose Processor (GPP) with performance of Application Specific Integrated Circuits (ASIC). There are several architectures proposed since RC’s inception in 1960s, but all have failed to become mainstream. The main factor preventing RC to become common practice is its requirement for implementers of algorithms (programmers) to be familiar with hardware design. In RC, a hardened processor cooperates with a dynamic reconfigurable Hardware Accelerator (HA) which is implemented on Field-Programmable Gate Array (FPGA). The HA implements crucial software kernel on hardware to increase performance and its design demands digital circuit expertise. In this paper a novel RC architecture is proposed that keeps the decades old programming practices intact while harnessing the power of HA. The architecture uses LLVM compiler infrastructure to receive an algorithm and then outputs the equivalent machine language, it then finds the most frequent instruction pairs and generates equivalent RC circuit called “Miniature Accelerator (MA)”. The instruction pairs are dynamically removed from pipeline and MA computed result replaces them in parallel. To demonstrate the concept the Fast Fourier Transform (FFT) algorithm which is core Digital signal processing (DSP) kernel is written in C and then executed on an ARM Cortex-M0. The execution of FFT function is improved by 14.12%. The proposed adaptive processor is fully backward compatible, compilation is automated, and no modification of exiting software or established programming paradigms is required.

show abstract

Implementation and Verification of IEEE-754 64-bit Floating-Point Arithmetic Library for 8-bit Soft-Core Processors

Cited by 5 publications

References 9 publications

A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture

A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture

Modular transformation of embedded systems from firm-cores to soft-cores

A morphable FPGA soft processor using LLVM infrastructure targeting low-power application-specific embedded systems

Contact Info

Product

Resources

About