Implementation and testing of multipliers using reversible logic

Babu, Y. Ratna; Syamala, Y.

doi:10.1049/ic.2011.0073

Cited by 7 publications

(1 citation statement)

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“…The main structures of the reversible gates are designed in such a way that the number of inputs is equal to the number of outputs. By this, it improves the overall performance of the systems [8]- [10]. In this paper systolic array multiplier is designed using reversible technology; it means all the components of the design use reversible gates to achieve the low power targets.…”

Section: Introductionmentioning

confidence: 99%

Design and testing of systolic array multiplier using fault injecting schemes

Jahagirdar

Rao

2022

Comput. Sci. Inf. Technol.

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Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low power appliances, faults and coverage of the reversible logic are calculated in this paper. To improvise more, we introduced a reversible logic gate and tested the reversible systolic array multiplier using the fault injection method of built-in self-test block observer (BILBO) in which all corner cases are covered which shows 97% coverage compared with existing designs. Finally, Xilinx ISE 14.7 was used for synthesis and simulation results and compared parameters with existing designs which prove more efficiency.

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Section: Introductionmentioning

confidence: 99%