Implementation and evaluation of a microthread architecture

Bousias, K.; Guang, Liang; Jesshope, Chris; Lankamp, M.

doi:10.1016/j.sysarc.2008.07.001

Cited by 31 publications

(18 citation statements)

References 10 publications

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“…Different simulators used in industry and academia with their simulation speed in terms of IPS are; COTSon [1] executes at 750KIPS, SimpleScalar [2] executes at 150KIPS, Interval simulator [5] executes at 350KIPS and Sesame [8] executes at 300KIPS. and MGSim [4] executes at 100KIPS. Compared to the IPS of these simulators the IPS of HLSim is very promising.…”

Section: E Ips -Simulation Speedmentioning

confidence: 99%

“…This model is called the microthreading model and is also applicable to current multi-core architectures using a library of the concurrency constructs called svp-ptl [35] built on top of pthreads. Our work focus on the microthreaded architecture where each core contains a single issue, in-order RISC pipeline with an ISA similar to DEC/Alpha, and all cores are connected to an on-chip distributed memory network [14], [4]. Each core implements the concurrency constructs in its ISA and is able to support hundreds of threads and their contexts, called microthreads and tens of families (i.e.…”

Section: Introductionmentioning

confidence: 99%

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High-level simulation of concurrency operations in microthreaded many-core architectures

Uddin¹

2015

GSTF J Comput

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Abstract-Computer architects are always interested in analyzing the complex interactions amongst the dynamically allocated resources. Generally a detailed simulator with a cycle-accurate simulation of the execution time is used. However, the cycleaccurate simulator can execute at the rate of 100K instructions per second, divided over the number of simulated cores. This means that the evaluation of a complex application with complex concurrency interactions on contemporary multi-core machine can be very slow. To perform efficient design space exploration we present a co-simulation environment, where the detailed execution of concurrency instructions in the pipeline of microthreaded cores and the interactions amongst the hardware components are abstracted. We present the evaluation of the high-level simulation framework against the cycle-accurate simulation framework. The results show that high-level simulator is faster and less complicated than cycle-accurate simulator and has reasonable accuracy.

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Section: E Ips -Simulation Speedmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

High-level simulation of concurrency operations in microthreaded many-core architectures

Uddin¹

2015

GSTF J Comput

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“…SVP [3], [4], [5] is a multi-core architecture and programming model that The first and the last thread in the previous process reads and writes values from and to the shared memory. The shared memory is used for the storage of scalar and array data.…”

Section: The Svp Modelmentioning

confidence: 99%

Ariadne — Directive-based parallelism extraction from recursive functions

Mastoras

Manis

2015

Journal of Parallel and Distributed Computing

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“…In our work, we focus on a specific implementation of the Microgrid architecture where each core contains a single-issue, in-order RISC pipeline with an ISA similar to DEC/Alpha, and all cores are connected to a on-chip shared memory network [9,2]. Each core implements the SVP actions in its instruction set and is able to support hundreds of threads and their contexts, called microthreads and tens of fami- High-level simulation of the microthreaded architecture lies (i.e.…”

Section: Motivation and Backgroundmentioning

confidence: 99%

“…Because of the multi-threaded nature of the core [2] instruction throughput is one cycle per instruction for all operations provided the sufficient number of active threads. However with a single thread the throughput is limited by the instruction latency.…”

Section: While(i<=10) If(condition)mentioning

confidence: 99%

Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores

Uddin

Jesshope

Tol

et al. 2012

Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

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Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores Irfan-Ud-Din, M.; Jesshope, C.R.; van Tol, M.W.; Poss, R.C. General rightsIt is not permitted to download or to forward/distribute the text or part of it without the consent of the author(s) and/or copyright holder(s), other than for strictly personal, individual use, unless the work is under an open content license (like Creative Commons). Disclaimer/Complaints regulationsIf you believe that digital publication of certain material infringes any of your rights or (privacy) interests, please let the Library know, stating your reasons. In case of a legitimate complaint, the Library will make the material inaccessible and/or remove it from the website. Please Ask the Library: http://uba.uva.nl/en/contact, or a letter to: Library of the University of Amsterdam, Secretariat, Singel 425, 1012 WP Amsterdam, The Netherlands. You will be contacted as soon as possible. ABSTRACTThe current many-core architectures are generally evaluated by a detailed emulation with a cycle-accurate simulation of the execution time. However this detailed simulation of the architecture makes the evaluation of large programs very slow. Since the focus in many-core architecture is shifting from the performance of the individual core to the overall behavior of chip, high-level simulations are becoming necessary, which evaluate the same architecture at less detailed level and allow the designer to make quick and reasonably accurate design decisions. We have developed a high-level simulator for the design space exploration of the Microgrid, which is a many-core architecture comprised of many finegrained multi-threaded cores. This simulator allows us to investigate mapping and scheduling strategies of families (i.e. groups of threads) in developing an operating environment for the Microgrid. The previous method to evaluate the workload counted in basic blocks was inaccurate. The key problem is that with many concurrent threads the latency of certain instructions are hidden because of the multithreaded nature of the core. This paper presents a technique to manage the execution time of different types of instructions with thread concurrency. We believe to achieve high accuracy in evaluating programs in the high-level simulator.

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Implementation and evaluation of a microthread architecture

Cited by 31 publications

References 10 publications

High-level simulation of concurrency operations in microthreaded many-core architectures

High-level simulation of concurrency operations in microthreaded many-core architectures

Ariadne — Directive-based parallelism extraction from recursive functions

Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores

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