Implementation and Applications of Tri-State Self-Organizing Maps on FPGA

Abstract

This paper introduces a tri-state logic Self Organising Map (bSOM) designed and implemented on a Field Programmable Gate Array (FPGA) chip. The bSOM takes binary inputs and maintains tri-state weights. A novel training rule is presented. The bSOM is well-suited to FPGA implementation, trains quicker than the original SOM, and can be used in clustering and classification problems with binary input data. Two practical applications, character recognition and appearance-based object identification, are used to illustrate the performance of the implementation. The appearance-based object identification forms part of an end-to-end surveillance system implemented wholly on FPGA. In both applications, binary signatures extracted from the objects are processed by the bSOM. The system performance is compared with a traditional SOM with real-valued weights and a strictly binary weighted SOM.

A Method for Detecting Abnormal Program Behavior on Embedded Devices

“…The proposed system naturally combines the embedded system's hardware and software together, introducing a new potential direction to secure an embedded device. In one of the authors' previous works [27], an implementation of the conventional SOM on a Xilinx Virtex-4 with 40 neurons required only 22.1% of the available 5,184 Kb Block RAM. The debug facility targeted for our initial on-chip prototyping is utilising a mid-range Xilinx Virtex-6 FPGA having 25,344 Kb (max.)…”

“…Again, the Virtex-4 design implementation clocked at 25MHz could train with approximately 10,000 patterns per second. As a result of this, the hardware implementation of the SOM produces a significant speed improvement, which is 30 times faster than the original SOM implemented on a state-of-art PC [27]. Hence, the preferred implementation is to follow a hardware acceleration approach that facilitated rapid SOM processing suitable for real-time execution.…”

Exploring ICMetrics to detect abnormal program behaviour on embedded devices

“…The proposed system can be run on a non-intrusive debug facility, a non-intrusive infrastructure that is generally used during device software development at present in all production devices, that connects to the targeted embedded device through a debug interface [28,29], which means that the proposed system would not affect the performance of the monitored embedded system in terms of additional memory and processor usage. In one of the authors' previous works [30], an implementation of the conventional SOM on a Xilinx Virtex-4 with 40 neurons required only 22.1% of the available 5,184 Kb Block RAM. Again, the Virtex-4 design implementation clocked at 25MHz could train with approximately 10,000 patterns per second.…”

“…Again, the Virtex-4 design implementation clocked at 25MHz could train with approximately 10,000 patterns per second. As a result of this, the hardware implementation of the SOM produces a significant speed improvement, which is 30 times faster than the original SOM implemented on a state-of-art PC [30]. Hence, the preferred implementation is to follow a hardware acceleration approach that facilitated rapid identification processing suitable for real-time execution.…”

A novel recursive algorithm used to model hardware programmable neighborhood mechanism of self-organizing neural networks

“…Hardware realization that are an alternative, usually mean Field Programmable Gate Arrays (FPGAs) [7][8][9][10] but also, more rarely, Application Specific Integrated Circuits (ASICs) realized in the 'full custom' style [8,[11][12][13][14]. A challenge in this case http://dx.doi.org/10.1016/j.amc.2015.03.068 0096-3003/Ó 2015 Elsevier Inc. All rights reserved.…”