Impact of weak Fermi-level pinning on the correct interpretation of III-V MOS C-V and G-V characteristics

Martens, Koen; Wang, W.; Keersmaecker, Kim De; Borghs, Gustaaf; Groeseneken, G.; Maes, H.E.

doi:10.1016/j.mee.2007.04.039

Cited by 59 publications

(36 citation statements)

References 2 publications

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“…Specifically, if the interface trap capacitance is larger than oxide capacitance, i.e., C ox Ͻ qD it , the measured impedance is dominated by the oxide capacitance and the D it is underestimated. 28,45 Finally, for 4C ox Ͻ qD it the extracted parallel conductance becomes insensitive to D it . 28,29,45 For example, the ͓͑G p / ͒ / Aq͔ max values measured at 300 K for the n-MOSCAP annealed in nitrogen shown in Fig.…”

Section: Issues and Limitationsmentioning

confidence: 95%

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Comparison of methods to quantify interface trap densities at dielectric/III-V semiconductor interfaces

Engel‐Herbert

Hwang

Stemmer

2010

Journal of Applied Physics

372

273

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Methods to extract trap densities at high-permittivity ͑k͒ dielectric/III-V semiconductor interfaces and their distribution in the semiconductor band gap are compared. The conductance method, the Berglund intergral, the Castagné-Vapaille ͑high-low frequency͒, and Terman methods are applied to admittance measurements from metal oxide semiconductor capacitors ͑MOSCAPs͒ with high-k / In 0.53 Ga 0.47 As interfaces with different interface trap densities. The results are discussed in the context of the specifics of the In 0.53 Ga 0.47 As band structure. The influence of different conduction band approximations for determining the ideal capacitance-voltage ͑CV͒ characteristics and those of the MOSCAP parameters on the extracted interface trap density are investigated. The origins of discrepancies in the interface trap densities determined from the different methods are discussed. Commonly observed features in the CV characteristics of high-k / In 0.53 Ga 0.47 As interfaces are interpreted and guidelines are developed to obtain reliable estimates for interface trap densities and the degree of Fermi level ͑un͒pinning for high-k / In 0.53 Ga 0.47 As interfaces.

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Section: Issues and Limitationsmentioning

confidence: 95%

“…28,45 Finally, for 4C ox Ͻ qD it the extracted parallel conductance becomes insensitive to D it . 28,29,45 For example, the ͓͑G p / ͒ / Aq͔ max values measured at 300 K for the n-MOSCAP annealed in nitrogen shown in Fig. 3 give a maximum D it near midgap of ϳ2 ϫ 10 13 cm −2 eV −1 .…”

Section: Issues and Limitationsmentioning

confidence: 95%

Comparison of methods to quantify interface trap densities at dielectric/III-V semiconductor interfaces

Engel‐Herbert

Hwang

Stemmer

2010

Journal of Applied Physics

372

273

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“…The thicker oxides show almost no frequency dispersion, except a frequency dependent flatband shift, which originates from the interface traps and may be a consequence of a weak Fermi level pinning. 25 For the thinner films, the C-V measurements in the accumulation regime additionally show a vertical shift with changing frequency, illustrating the growing influence of the interface trap density on the C-V behavior. The respective EOTs of all processed stacks have been extracted from the 50 kHz C-V data by the Hauser CVC-software, 26 and are plotted in Fig.…”

mentioning

confidence: 87%

Atomic layer deposition of ZrO2/La2O3 high-k dielectrics on germanium reaching 0.5 nm equivalent oxide thickness

Abermann

Bethge

Henkel

et al. 2009

Applied Physics Letters

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We investigate ultrathin ZrO2/La2O3 high-k dielectric stacks on germanium grown by atomic layer deposition. La2O3 is deposited from tris(N,N′-diisopropylformamidinate)-lanthanum and oxygen. Interfacial layer-free oxide stacks with a relative dielectric constant of 21 and equivalent oxide thickness values as low as 0.5 nm are obtained. Metal oxide semiconductor capacitors with platinum as the gate electrode exhibit well-behaved capacitance-voltage characteristics, gate leakage current densities in the range of 0.01–1 A/cm2, and interface trap densities in the range of ∼3×1012 eV−1 cm−2.

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“…First, the presence of a high D it at the dielectric/GaAs interface is a possible 2015) explanation for the origin of the accumulation dispersion; n-type GaAs MOS capacitors displayed D it -dominant C-V curves governed by weak Fermi level pinning. [48][49][50] Introduction of the AlN passivation led to the incorporation of nitrogen at the interface as shown in Figure 6. Guo et al proposed a nitrogen passivation mechanism, 38,13 whereby nitrogen at the Al 2 O 3 /GaAs interface can replace interfacial arsenic (As), leading to the efficient removal of problematic As dimers or As-dangling bond states.…”

Section: Characterization Of Electrical Properties Of Al 2 O 3 / Amentioning

confidence: 99%

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

et al. 2015

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This paper presents a compressive study on the fabrication and optimization of GaAs metal–oxide–semiconductor (MOS) structures comprising a Al2O3 gate oxide, deposited via atomic layer deposition (ALD), with an AlN interfacial passivation layer prepared in situ via metal–organic chemical vapor deposition (MOCVD). The established protocol afforded self-limiting growth of Al2O3 in the atmospheric MOCVD reactor. Consequently, this enabled successive growth of MOCVD-formed AlN and ALD-formed Al2O3 layers on the GaAs substrate. The effects of AlN thickness, post-deposition anneal (PDA) conditions, and crystal orientation of the GaAs substrate on the electrical properties of the resulting MOS capacitors were investigated. Thin AlN passivation layers afforded incorporation of optimum amounts of nitrogen, leading to good capacitance–voltage (C–V) characteristics with reduced frequency dispersion. In contrast, excessively thick AlN passivation layers degraded the interface, thereby increasing the interfacial density of states (Dit) near the midgap and reducing the conduction band offset. To further improve the interface with the thin AlN passivation layers, the PDA conditions were optimized. Using wet nitrogen at 600 °C was effective to reduce Dit to below 2 × 1012 cm−2 eV−1. Using a (111)A substrate was also effective in reducing the frequency dispersion of accumulation capacitance, thus suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. The current findings suggest that using an atmosphere ALD process with in situ AlN passivation using the current MOCVD system could be an efficient solution to improving GaAs MOS interfaces.

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Impact of weak Fermi-level pinning on the correct interpretation of III-V MOS C-V and G-V characteristics

Cited by 59 publications

References 2 publications

Comparison of methods to quantify interface trap densities at dielectric/III-V semiconductor interfaces

Comparison of methods to quantify interface trap densities at dielectric/III-V semiconductor interfaces

Atomic layer deposition of ZrO2/La2O3 high-k dielectrics on germanium reaching 0.5 nm equivalent oxide thickness

Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

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