Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment

Gimenez, Salvador Pinillos; Galembeck, Egon Henrique Salerno; Renaux, Christian; Flandre, Denis

doi:10.1109/tdmr.2015.2474739

Cited by 12 publications

(6 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The fully-depleted SOI CMOS manufacturing process used was of 2 µm, notably optimized for high-temperature operation and analog applications at voltages higher than 3 V. The main technological parameters of these SOI MOSFETs are: the gate oxide thickness (tox), the silicon film thickness (tSi), and the buried oxide thickness (tBox) are equal to 30 nm, 80 nm and 390 nm, respectively. The concentrations of acceptors impurities in the channel region is 6x10 16 cm -3 and the donors impurities in the regions drain and source are equal to 1x10 20 cm -3 [31,32].…”

Section: Device's Characteristics and Structuresmentioning

confidence: 99%

See 1 more Smart Citation

Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment

Galembeck

Flandre

Renaux

et al. 2019

JICS

Self Cite

View full text Add to dashboard Cite

This present paper performs an experimental comparative study of the main digital parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named OCTO SOI MOSFETs (OSM) in comparison with the typical rectangular one at high temperature environments. The devices were manufactured with the 1 mm SOI (CMOS) technology. The results demonstrate that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), the PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE) at high temperature conditions. Therefore, the OSM is able to continue to have a better electrical performance than the one found in the rectangular SOI MOSFET (RSM) counterparts, regarding the same gate areas and bias conditions. To illustrate, its on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller in relation to its RSM counterparts at high temperature conditions.

show abstract

Section: Device's Characteristics and Structuresmentioning

confidence: 99%

“…Four prior experimental studies describe in detail the better electrical performance of the DSM [14,30] and OSM [31,32], mainly regarding analog CMOS ICs applications operating at high-temperature environment, in relation to the traditional rectangular MOSFET counterpart.…”

Section: Introductionmentioning

confidence: 99%

Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment

Galembeck

Flandre

Renaux

et al. 2019

JICS

Self Cite

View full text Add to dashboard Cite

show abstract

“…A temperaturedependent SOI MOSFET compact model has been developed in [22], considering the existing temperature dependence of device parameters, but only for long-channel MOSFETs based on old technology processes. Other hightemperature specific issues have been addressed by Denis Flandre et al in [23], where low-frequency noise in submicron SOI devices has been characterized up to 230°C, and in [24], where special transistor layout geometries have been investigated to counteract the increase in leakage current at high temperature.…”

Section: Introductionmentioning

confidence: 99%

Design Criteria of High-Temperature Integrated Circuits Using Standard SOI CMOS Process up to 300°C

Sbrana,

Catania,

Paliy

et al. 2024

IEEE Access

View full text Add to dashboard Cite

In this paper, we discuss the challenges at the device and circuit level that must be addressed to design reliable silicon CMOS integrated circuits operating in high-temperature environments. We present experimental results on representative devices fabricated with a 180 nm CMOS SOI platform, which have been characterized up to 300°C, discuss issues arising at high temperature, and propose possible solutions. A BJT-based temperature sensor core is also described and evaluated across the same extended temperature range. We also propose and discuss design criteria optimized for a wide range of operating temperature. A sufficient on/off current ratio can be achieved by taking advantage of the isolation provided by low-leakage CMOS SOI process, while operation at low current density must be ensured to mitigate electromigration effects. Within these conditions, low-power precise sensing circuits can be effectively implemented with operating temperature up to 300°C, that are extremely relevant for industrial, mobility, and space applications.INDEX TERMS High temperature electronics; harsh environment electronics; CMOS SOI.

show abstract

“…; however, all of them involve high investments. Another low-cost alternative, not yet widespread in semiconductors and integrated circuits (ICs) industries, is to use nonconventional gate shapes [5] (Diamond/hexagonal [6], Octagonal [7], Ellipsoidal [8]) for MOSFETs. This layout approach is capable of boosting the analog and digital electrical performances, including ionizing radiation tolerance of MOSFETs, thanks to the: I-"Longitudinal Corner Effect" (LCE), which is responsible for boosting the resultant longitudinal electric field (RLEF) in the channel region of the MOSFET and consequently its drift velocity [𝜗 ⃗ =.𝐿𝐸𝐹 ⃗⃗⃗⃗⃗⃗⃗⃗⃗ , where  is the average value of the mobility of mobile charge carriers along the channel (Qmcc)], and subsequently the drain to electric current source (𝐼 𝐷𝑆 ⃗⃗⃗⃗⃗⃗ = 𝑄𝑚𝑐𝑐.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, the electric current between the regions of the drain and source (IDS) of the MOSFET tends to further flow by the edges of the channel (infinitesimal CMs with the smallest channel lengths); III-"Deactivation of Parasitic MOSFETs in Bird's Beaks Regions" (DEPAMBBRE), which is capable of improving the ionizing radiation tolerance of the Total Ionizing Dose (TID) of MOSFETs, as the RLEF lines are curves in the edges of the channel of the MOSFET. Consequently, they are able to deactivate the parasitic MOSFETs in the Bird's Beak region [6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs

DaSilva

Gimenez

2022

JICS

View full text Add to dashboard Cite

Previous studies have been showing that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal) and Ellipsoidal gate shapes for implementing of the planar and three-dimensional MOSFETs are is capable of boosting their analog and digital electrical performances and also by reducing used die areas, when we replace conventional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), that present rectangular gate shape, by those implemented by these innovative layout styles. In order to further boosting these features obtained by the use of first generation of layout styles, we are introducing one of elements of the second generation of layout styles for MOSFETs, intitled Half-Diamond. This new proposal is an evolution of Diamond layout style, in which it is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivation of Parasitic MOSFETs in Bird’s Beaks Regions (DEMPAMBBRE) effects of the first generation and also of further reducing the dimensions of conventional MOSFETs (CM) in which the Diamond MOSFETs have gotten to do. Thus, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond and Conventional layout styles, regarding the analog Complementary MOS (CMOS) integrated circuits (ICs) applications, which their channel lengths are not usually designed with the minimum dimension (Lmin) allowed by the CMOS ICs manufacturing processes. The results obtained show that, for instance, the saturation drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in CM counterparts. Besides, by using Half-Diamond layout style, it is possible of further reducing the die areas of analog CM and consequently of the analog CMOS ICs applications, in comparison to those reached by the use of Diamond layout styles, regarding a 180 nm Bulk CMOS ICs technology node.

show abstract

Impact of Using the Octagonal Layout for SOI MOSFETs in a High-Temperature Environment

Cited by 12 publications

References 12 publications

Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment

Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment

Design Criteria of High-Temperature Integrated Circuits Using Standard SOI CMOS Process up to 300°C

Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs

Contact Info

Product

Resources

About