Impact of traps on DC, analog/RF, and linearity performance of Ferro-TFET

Das, Basab; Bhowmick, Brinda

doi:10.1007/s12633-022-02167-8

Cited by 4 publications

(1 citation statement)

References 52 publications

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“…Recently, researchers are looking towards non-volatile information devices with low power consumption, such as tunnel FETs [1][2][3][4] and negative capacitance FETs [5,6] for logic application and ferroelectric FETs (FeFETs) for memory application. FeFETs have been attracting much attention in non-volatile memory (NVM) application due to the advantages of the scalability and CMOS compatibility for hafniabased ferroelectric material [7][8][9][10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

Temperature effects on the performance of ferroelectric FET with random grain phase variation for non-volatile memory application

Hsu

et al. 2023

Semicond. Sci. Technol.

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We report the temperature effects on the performance of ferroelectric field-effect transistor(FeFET) based non-volatile memory (NVM) considering random grain phase variation in the ferroelectric layer through simulation. Based on the FE temperature effect model that accounts for both the transistor and ferroelectric degradation, we demonstrate that: 1) at a certain temperature, the memory window (MW) decreases with pronounced effect on low threshold voltage shift and its variation increases as the FE phase decreases; 2) with the temperature increases, the MW decreases with pronounced effect on high threshold voltage shift. The random grain phase variation further exacerbates the MW distribution, thus degrading the sensing margin. These results may provide insights for device design of high-performance FeFET-based NVMs.

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