Impact of the NO annealing duration on the SiO2/4H–SiC interface properties in lateral MOSFETs: The energetic profile of the near-interface-oxide traps

Fiorenza, Patrick; Zignale, Marco; Camalleri, Marco; Scalia, Laura; Zanetti, Edoardo; Saggio, Mario; Giannazzo, Filippo; Roccaforte, Fabrizio

doi:10.1016/j.mssp.2023.107866

Cited by 2 publications

(1 citation statement)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The n-type drift epitaxial layer is 12 µm thick with a nitrogen-doping concentration of 8 × 10 15 cm −3 and is grown by chemical vapor deposition (CVD) in a warm wall multi-wafer reactor. The gate insulation layer is a 50 nm thick deposited oxide layer through a Low-Pressure Chemical Vapor Deposition (LPCVD) process followed by a state-of-the-art NO-based post-oxide deposition annealing [22]. The semiconductor materials were characterized at the beginning of the device fabrication process using microscopic techniques in order to select those devices without any visible epitaxial defect that may affect the device's reliability [12,23].…”

Section: Methodsmentioning

confidence: 99%

4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed High-Temperature Reverse Bias and Negative Gate Bias Stresses

Anoldo,

Zanetti,

Coco

et al. 2024

Materials

Self Cite

View full text Add to dashboard Cite

This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO2 interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler–Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions. Moreover, it has been demonstrated from the cross-correlation, the TCAD simulation, and the experimental ΔVth and ΔVFN variation that HTGB stress is more severe compared to HTRB. In fact, HTGB showed a 15% variation in both ΔVth and ΔVFN, while HTRB showed only a 4% variation in both ΔVth and ΔVFN. The physical explanation was attributed to the accelerated degradation of the gate insulator in proximity to the source region under HTGB configuration.

show abstract

Section: Methodsmentioning

confidence: 99%