Impact of temperature variation on noise parameters and HCI degradation of Recessed Source/Drain Junctionless Gate All Around MOSFETs

Kumar, Alok; Gupta, Tarun Kumar; Shrivastava, Bhavana P.; Gupta, Abhinav

doi:10.1016/j.mejo.2023.105720

Cited by 11 publications

(3 citation statements)

References 22 publications

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“…Table 3 compares the electrical performance of I-JL-NWFET with JL-NWFET, experimental work [10], Recessed Source/Drain Junctionless Gate All Around (Re-S/D-JL-GAA) MOSFET [36] and Dielectric Pocket Gate All Around (DPGAA) MOSFET [37]. It can be observed that I-JL-NWFET showcases higher I ON /I OFF , and less value of I OFF , SS and DIBL when compared to other published work.…”

Section: Impact Of Channel Thickness Scaling On Electrical Parametersmentioning

confidence: 96%

Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis

Bharti,

Mittal

2024

Phys. Scr.

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An Improved Junctionless Nanowire Field Effect Transistor (I-JL-NWFET) device is proposed in this paper to address the limitations of conventional JL-NWFET. This research paper initially, comprehensively analyzes the impact of channel length (L) and channel thickness (t si ) scaling on the electrical, analog/RF, and linearity performance of I-JL-NWFET and JL-NWFET. The results suggest that the specific design features in I-JL-NWFET contribute to a more robust and less sensitive response to variations in scaling compared to its counterpart, JL-NWFET. Furthermore, an exploration into the impact of temperature on the electrical, analog/RF, and linearity performance is also conducted for both I-JL-NWFET and JL-NWFET. The electrical performance of I-JL-NWFET showcases a significantly reduced temperature sensitivity in parameters like drain current (I D ), Subthreshold Slope (SS) and Drain Induced Barrier Lowering (DIBL) compared to JL-NWFET. Subsequently, analyzing the analog/RF performance in the context of parameters such as transconductance (g m ), Transconductance Gain Factor (TGF), output conductance (g d ), early voltage (V EA ), total gate capacitance (C GG ), and cut-off frequency (f T ) under temperature variation, a lower degree of variability in I-JL-NWFET is observed compared to JL-NWFET. Furthermore, the linearity performance of I-JL-NWFET, assessed through parameters such as second and third-order transconductance (g m2 , g m3 ), second and third-order input voltage intercept points (VIP2, VIP3), and third-order intermodulation distortion (IIP3 and IMD3) is improved at the higher temperature than that of JL-NWFET.

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Section: Impact Of Channel Thickness Scaling On Electrical Parametersmentioning

confidence: 96%

Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis

Bharti,

Mittal

2024

Phys. Scr.

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“…Silicon-based piezoresistive sensing elements are generally used in various types of pressure sensing applications, such as blood pressure monitoring and fuel pressure measuring in automobiles [1,2], which is the first piezoresistive sensing element in the micro-electromechanical system device. Recently, the silicon nanowire gate-all-around (GAA) field-effect transistors (FETs) have been used for enhancing the piezoresistive sensitivity by tuning the channel conductivity via gate bias [3], but they suffer higher electronic noise [4,5] and electrothermal reliability issues [6,7]. However, the junctionless nanowire (JL-NW) GAA FETs were shown to have better performance * Author to whom any correspondence should be addressed.…”

Section: Introductionmentioning

confidence: 99%

Piezoresistive sensitivity enhancement below threshold voltage in sub-5 nm node using junctionless multi-nanosheet FETs

Kumar,

Joshi,

Gupta

et al. 2024

Nanotechnology

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In this paper, the piezoresistive sensitivity is enhanced by applying uniform mechanical stress (MS) on the multi-nanosheet (NS) channels of sub-5 nm junctionless field-effect transistors (FETs). The piezoresistivity of the sensing device is boosted by narrowing channel conductivity using low gate biasing and reducing physical channel width, resulting in the maximum (~6 times higher) sensitivity observed in the subthreshold regime compared to the ON-state condition. In addition, the sensitivity is extensively increased by ~30.3% near the threshold voltage (VTH) with horizontally multi-NS stacking due to the uniform MS distribution on the multi-NS channels, which can sense slight deflection of pressure on the circular diaphragm. These results show that the tunable sensitivity of junctionless multi-channel devices is superior to the inversion mode, a consequence of the less scattering effect, better thermal stability, and low electronic noise.

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“…Pushpraj S. et al [20] experimentally demonstrated in GAA JLFET that, low frequency noise (LFN) is low and independent of gate bias owing to less encounter of carriers with interface in the course of travelling across silicon body. Alok K. et al [21] performed the noise analysis on recessed source/drain junctionless GAA (Re-S/D-JL-GAA) and junctionless GAA (JL-GAA) MOSFET and found that noise parameters are minimum for JL-GAA MOSFET compared to the Re-S/D-JL-GAA MOSFET. Extensive noise models are necessary for the characterization of the device from low to high frequency range, owing to meagre literature and discussion on noise characteristics especially for devices based on negative capacitance, to be employed in analog circuits [11].…”

Section: Introductionmentioning

confidence: 99%

Noise analysis of NC-GAAFET cylindrical nanowire with non-uniform interface trap charge

Kumar,

Maurya,

Rawat

et al. 2024

Phys. Scr.

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In this article, low to high frequency noise behavior analysis of negative capacitance gate-all-around field effect transistor (NC-GAAFET) MFIS structure Silicon Nanowire (SiNW) device, using Sentauras TCAD simulations, is investigated. The NC-GAAFET SiNW yields on current (ION) 5.31 times larger and off current (IOFF) is significantly reduced by ∼ 105 orders compared to baseline SiNW. The device exhibits an excellent switching ratio of 5.2 × 1014. Average subthreshold swing for the NC-GAAFET is 33 mV/dec compared to 64 mV/dec of baseline nanowire. The Negative-DIBL for the device is −20 mV/V which outshines earlier findings. Furthermore, the drain current noise power spectral density (PSD) Sid, and input referred gate voltage noise PSD (Svg) are comprehensively analyzed in the presence of Gaussian trap (non-uniform) distribution. The analysis indicates that, flicker or (1/f) noise dominates in low frequency regime, generation-recombination (G-R) noise is more influential in mid frequency regime whereas in very high frequency regime diffusion noise is leading. The device exhibits least Sid(NET) and Svg(NET) at tfe = 6 nm compared to baseline, tfe = 5 nm, and 7 nm.

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Impact of temperature variation on noise parameters and HCI degradation of Recessed Source/Drain Junctionless Gate All Around MOSFETs

Cited by 11 publications

References 22 publications

Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis

Investigating the effect of scaling and temperature on the performance of improved junctionless nanowire FET through simulation analysis

Piezoresistive sensitivity enhancement below threshold voltage in sub-5 nm node using junctionless multi-nanosheet FETs

Noise analysis of NC-GAAFET cylindrical nanowire with non-uniform interface trap charge

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