Impact of temperature counting the effect of back gate bias on the performance of extended source tunnel FET (ESTFET) with δp+ SiGe pocket layer

Talukdar, Jagritee; Choudhuri, Bijit; Mummaneni, Kavicharan

doi:10.1007/s00339-020-04164-3

Cited by 7 publications

(2 citation statements)

References 21 publications

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“…In case of the double gate different electrical parameters have been changed because of the application of the back-gate potential which results in more inversion charge carrier due to back gate-BOX-channel interface. A detailed analysis of the impact of back gate on the ES-TFET structure has been provided in [6,12]. The basic fabrication steps for the device started with growing the structure on a buried oxide (BOX).…”

Section: Device Structure and Simulation Methodologiesmentioning

confidence: 99%

“…This leads to the degraded voltage gain as well as noise margins of digital inverters. Further, the temperature variation of TFET based device has been explored in literature which showed that TFET has better temperature immunity as compared to MOSFET and other reported devices [6][7][8]. In previous study it has been shown that by enabling the trap assisted tunneling and SRH mechanism which are highly dependent on temperature TFET parameters can achieve a higher immunity against temperature.…”

Section: Introductionmentioning

confidence: 99%

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Source engineered TFET for digital inverters application

Talukdar,

Malvika,

Das

et al. 2024

Phys. Scr.

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This article delves into a performance evaluation of source engineered asymmetric Tunnel Field Effect Transistors using Sentaurus TCAD. The focus of this analysis centers around Single and Double gate extended Source TFET (SG-ESTFET and DG-ESTFET) device configurations. The study emphasizes the reliability of these devices for circuit applications taking in account interface trap charges. Various digital inverters based on the aforementioned TFET devices are designed, showcasing their potential utility in terms of different delay parameters. Additionally, the article explores transient characteristics and notes the occurrence of undershoot when interface trap charges are present at oxide-semiconductor interfaces. Notably, the findings indicate that DG-ESTFET surpasses SG-ESTFET in mitigating undershoot, and the measured propagation delay is reported to be 9 ps.

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Section: Device Structure and Simulation Methodologiesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Source engineered TFET for digital inverters application

Talukdar,

Malvika,

Das

et al. 2024

Phys. Scr.

Self Cite

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Advanced 18 nm FinFET Node-Based Energy Efficient and High-Speed Data Comparator Using SR Latch

Lavanya

Priya

Janet

et al. 2022

Lecture Notes in Electrical Engineering

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A Reliability Study of Non-uniform Si TFET with Dual Material Source: Impact of Interface Trap Charges and Temperature

Talukdar

Mummaneni

2021

Silicon

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The article reports the extraction of DC characteristics and small signal parameters of Non-uniform Si TFET with dual material source (NUTFET-DMS) at different frequencies followed by its reliability investigation. The reliability of the device is examined by analysing: 1) the impact of the presence of interface trap charges, 2) the impact of temperature variation (200 K-400 K). In the analysis it has been observed that in case of absence of interface trap charges the increase in frequency reduces the value of parasitic capacitances. In addition, the presence of interface trap charges lessens the value of parasitic capacitances up to a certain gate to source voltage after that it shows a reverse effect. Further, it has been perceived that the effect of change in temperature is more on device ambipolar current when interface trap charges are present, whereas the reverse is true in the case of OFF state current and different parasitic capacitances.

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Impact of temperature counting the effect of back gate bias on the performance of extended source tunnel FET (ESTFET) with δp+ SiGe pocket layer

Cited by 7 publications

References 21 publications

Source engineered TFET for digital inverters application

Source engineered TFET for digital inverters application

Advanced 18 nm FinFET Node-Based Energy Efficient and High-Speed Data Comparator Using SR Latch

A Reliability Study of Non-uniform Si TFET with Dual Material Source: Impact of Interface Trap Charges and Temperature

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