Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells

Abbas, Zia; Olivieri, Mauro

doi:10.1016/j.mejo.2013.10.013

Cited by 50 publications

(25 citation statements)

References 16 publications

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“…In ASIC implementation, the performance data is extracted from the reported results in [4], [6] with the following technology scaling: Area ∼ 1/S 2 , Delay ∼ 1/S 2 , Energy ∼ 1/S, where S = L/32nm and leakage scaling factor from [36]. The stacked CMOL AES performance is projected from [7].…”

Section: Aes Performance Comparisonmentioning

confidence: 99%

DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory

Wang

Chang

et al. 2016

IEEE Trans.Inform.Forensic Secur.

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Big-data storage poses significant challenges to anonymization of sensitive information against data sniffing. Not only will the encryption bandwidth be limited by the I/O traffic, the transfer of data between processor and memory will also expose the input-output mapping of intermediate computations on I/O channels that are susceptible to semi-invasive and noninvasive attacks. Limited by the simplistic cell-level logic, existing logic-in-memory computing architectures are incapable of performing the complete encryption process within the memory at reasonable throughput and energy efficiency. In this paper, a block-level in-memory architecture for Advanced Encryption Standard (AES) is proposed. The proposed technique, called DW-AES, maps all AES operations directly to the domainwall nanowires. The entire encryption process can be completed within a homogeneous, high-density and standby-power-free non-volatile spintronic based memory array without exposing the intermediate results to external I/O interface. Domain-wall nanowires based pipelining and multi-issue pipelining methods are also proposed to increase the throughput of the baseline DW-AES with insignificant area overhead and negligible difference on leakage power and energy consumption. The experimental results show that DW-AES can reduce the leakage power and area by orders of magnitude compared to existing CMOS ASIC accelerators. It has an energy efficiency of 22 pJ/bit, which is 5× and 3× better than the CMOS ASIC and memristive CMOL based implementations, respectively. Under the same area budget, the proposed DW-AES achieves 4.6× higher throughput than the latest CMOS ASIC AES with similar power consumption. The throughput improvement increases to 11× for pipelined DW-AES at the expense of doubling the power consumption.

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Section: Aes Performance Comparisonmentioning

confidence: 99%

DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory

Wang

Chang

et al. 2016

IEEE Trans.Inform.Forensic Secur.

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“…In fact, extensive work has been explored on the impact of variability on propagation delay and leakage power [3] address the impact of statistical process variations and NBTI aging on the WNMs and consequently on the probability of write failures in register cells (flip-flops) used in semi-custom digital design. Our focus is on local cell-level variations in equivalent oxide thickness (toxe), channel width (W) and length (L) for CMOS cells, and equivalent oxide thickness (toxe) 2 , channel length (L), fin height (hfin) and fin thickness (tfin) for FinFET cells.…”

Section: Background and Related Workmentioning

confidence: 99%

“…3 Technical documents report 5% as well as 10%, depending on the target degree of tolerance assumed for the cell library.…”

Section: B Calculation Of the Probability Of Write Failuresmentioning

confidence: 99%

Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops

Khalid

Mastrandrea

Olivieri

2015

Microelectronics Reliability

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“…In nano scale CMOS circuit design there are two types of power consumption static power which flow in when circuit is in ideal condition and dynamic power when circuit has switching. For the decade getting high performance, high packing density and low power reducing the transistor size scaling is required [5]. The technology is continuously and rapidly evolving the production of smaller systems with minimized power dissipation.…”

Section: Introductionmentioning

confidence: 99%

A New Technique for Leakage Power Reduction in CMOS circuit by using DSM

Rathore¹,

Kumre²

2017

IJCA

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In the continuous scaling down of technology in the field of integrated circuits, low power circuits are in demand for reliability and performance. This research focuses on run time leakage reduction technique for CMOS devices, this work introduces two well known approaches, stack approach with pass transistor approach for reduction of the leakage power and improves the performance of the circuit. Here NMOS transistor and PMOS transistor parallel to each other in between pull up and pull down network, the resistance is increased by providing stacking of the transistor for mitigation of leakage power. For proper validation and verification of results we use the module of proposed NAND gate to built a Full Adder circuit and for verification of results. Here NMOS pass transistor is connected between pull up network and pull down network similarly PMOS transistor is also connected between pull up network and pull down netwotk both NMOS and PMOS pass transistor are self controlling transistor whch reduces the power consumption in active and ideal mode at 43.33%, 43.33%, 86.07% and 86.04% at 25oC respectively as compared with the standard 2 input NOT,AND,NAND and NOR gates. Average dynamic power is reduced to 14.34%, 14.34%, 34.69%, 30.68% respectively.

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Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells

Cited by 50 publications

References 16 publications

DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory

DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory

Effect of NBTI/PBTI aging and process variations on write failures in MOSFET and FinFET flip-flops

A New Technique for Leakage Power Reduction in CMOS circuit by using DSM

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