Impact of technology scaling and process variations on RF CMOS devices

Hassan, Hassan; Anis, Mohab; Elmasry, M.I.

doi:10.1016/j.mejo.2005.07.013

Cited by 10 publications

(5 citation statements)

References 20 publications

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“…C MOS has emerged as leading candidates for RF applications due to the continued scaling resulting in extremely high unity-gain frequencies of tens to hundreds of gigahertz [1]. To develop a low-noise RF circuit, high-frequency noise modeling is essential, especially for nanometer MOSFETs.…”

Section: Introductionmentioning

confidence: 99%

Substrate-Induced Noise Model and Parameter Extraction for High-Frequency Noise Modeling of Sub-Micron MOSFETs

Ong

Yeo

Chew

et al. 2014

IEEE Trans. Microwave Theory Techn.

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In this paper, a substrate-induced drain-current noise model is developed in addition to the channel thermal noise to explain the non-white-noise characteristic found in the measured drain-current noise in the gigahertz range. The substrate-induced drain-current noise model is derived from the proposed small-signal equivalent circuit with a substrate coupling network and a substrate thermal noise source. The model parameter extraction method utilizing -parameter analysis on the proposed small-signal equivalent circuit is demonstrated. The model for the total drain-current noise, the gate-current noise, their cross-correlation, and thereafter the four noise parameters is presented and verified experimentally. Excellent agreement between simulated and measured noise data has been obtained over different dimensions and operating conditions. Index Terms-Channel thermal noise, high-frequency noise modeling, gate-current noise, MOSFET, substrate-induced drain-current noise, substrate noise, thermal noise. 0018-9480

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Section: Introductionmentioning

confidence: 99%

Substrate-Induced Noise Model and Parameter Extraction for High-Frequency Noise Modeling of Sub-Micron MOSFETs

Ong

Yeo

Chew

et al. 2014

IEEE Trans. Microwave Theory Techn.

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“…The procedure is described as follows: [17] are used for developing non-linear models that relate the DUT response to the process parameters. The MARS algorithm mainly depends on selection of a good set of basis functions based on the data at hand; at the same time adjustment of the coefficient values of the basis functions to best fit the data.…”

Section: B Test Generation Proceduresmentioning

confidence: 99%

Concurrent process model and specification cause-effect monitoring using alternate diagnostic signatures

Devarakond

Sen

Bhattacharya

et al. 2010

2010 28th VLSI Test Symposium (VTS)

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With technology scaling, the impact of intra and inter-die process variations on the performance of mixed-signal/RF circuits has increased, making process monitoring a critical task in the overall silicon manufacturing flow. We propose a novel processspecification cause-effect monitoring scheme that allows the effects of process variations and shifts on device specifications to be monitored on a per-IC basis as opposed to existing techniques that rely only on electrical test data gathered across lots of wafers. The method relies on the use of alternate diagnostic tests under which the DUT response (alternate diagnostic signature) exhibits strong simultaneous correlation with its specifications as well as the critical process or circuit parameters with virtually zero extra test-time or testhardware cost. Simulation results indicate that critical process parameters can be diagnosed accurately from the applied tests.

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“…[1] The improvements of these characteristics mainly rely on reductions of intrinsic gate capacitances in a MOSFET. [2,3] These intrinsic gate capacitances can be classified into total gate capacitance (𝐶 gg ) and gate transcapacitances, and the gate trans-capacitances include gate-to-source (𝐶 gs ), gate-to-bulk (𝐶 gb ), and gateto-drain (𝐶 gd ) capacitances. Based on the Meyer model, 𝐶 gg is the sum of 𝐶 gs , 𝐶 gd , and 𝐶 gb , i.e., 𝐶 gg = 𝐶 gs + 𝐶 gd + 𝐶 gb .…”

mentioning

confidence: 99%

“…On the other hand, these ultra-small gate capacitances are susceptible to the imperfect manufacture process, and any variations of a gate trans-capacitance will affect 𝐶 gg and the device characteristics. [2,4] Therefore, analysis and modeling of variations in these gate capacitances become an urgent task for predicting MOSFETs' behavior in the early design stage. [5,6] It has been reported that 𝐶 gg will vary drastically due to random dopant fluctuation (RDF) [7,8] in the MOSFET channel, which is regarded as one of the most important variation sources in current planar nanometer complementary metaloxide-semiconductor (CMOS) technology.…”

mentioning

confidence: 99%

Statistical Modeling of Gate Capacitance Variations Induced by Random Dopants in Nanometer MOSFETs Reserving Correlations

Lü

Wang

Lin

et al. 2015

Chinese Phys. Lett.

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We consider intrinsic gate capacitance variations due to random dopants in the nanometer metal oxide semiconductor field effect transistor (MOSFET) channel. The variations of total gate capacitance and gate transcapacitances are investigated and the strong correlations between the trans-capacitance variations are discovered. A simple statistical model is proposed for accurately capturing total gate capacitance variability based on the correlations. The model fits very well with the Monte Carlo simulations and the average errors are −0.033% for n-type metal-oxide semiconductor and −0.012% for p-type metal-oxide semiconductor, respectively. Our simulation studies also indicate that, owing to these correlations, the total gate capacitance variability will not dominate in gate capacitance variations.

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Impact of technology scaling and process variations on RF CMOS devices

Cited by 10 publications

References 20 publications

Substrate-Induced Noise Model and Parameter Extraction for High-Frequency Noise Modeling of Sub-Micron MOSFETs

Substrate-Induced Noise Model and Parameter Extraction for High-Frequency Noise Modeling of Sub-Micron MOSFETs

Concurrent process model and specification cause-effect monitoring using alternate diagnostic signatures

Statistical Modeling of Gate Capacitance Variations Induced by Random Dopants in Nanometer MOSFETs Reserving Correlations

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