Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility

Xiong, Wenjing; Cleavelin, C.R.; Kohli, Puneet; Huffman, C.; Schulz, T.; Schruefer, K.; Gebara, G.; Mathews, K.; Patruno, P.; Vaillant, Y.-M. Le; Cayrefourcq, I.; Kennard, M.; Mazuré, C.; Shin, Ki Soon; Liu, T.-J.K.

doi:10.1109/led.2006.877714

Cited by 71 publications

(30 citation statements)

References 14 publications

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“…This result indicates that the carrier mobility improvement provided by the strained material depends on the crystal orientation, as previously demonstrated in Ref. [18]. When W Fin is agressively reduced, the strain component perpendicular to the channel relaxes transforming the overall strain from biaxial to uniaxial, affecting the g m,max gain.…”

Section: Basic Device Characteristicssupporting

confidence: 78%

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

Pavanello

Martino

Simoen

et al. 2008

Solid-State Electronics

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Section: Basic Device Characteristicssupporting

confidence: 78%

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

Pavanello

Martino

Simoen

et al. 2008

Solid-State Electronics

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“…The combination of the global and local strained Si technologies is considered effective to induce extremely large strain in Si. Fin-type structures have been reported for high-performance FETs [13]. It is considered that the stress relaxation occurs during the fabrication of the fin-shaped strained Si layer.…”

Section: Introductionmentioning

confidence: 99%

Stress Measurements in Si and SiGe by Liquid-Immersion Raman Spectroscopy

Kosemura¹,

Tomita²,

Usuda³

et al. 2012

Advanced Aspects of Spectroscopy

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“…For the attached multi-gate devices to the BOX layer (e.g. Fin-FET but not GAA), four stressor technologies have been reported until now: epitaxial films in the S/D [22,23], CESL [24], strained substrate [25] and metal gate strain [26].…”

Section: Introduction To the Available Stressor Technologiesmentioning

confidence: 99%

Asymmetrically strained all-silicon multi-gate n-Tunnel FETs

Najmzadeh

Boucart

Rieß

et al. 2010

Solid-State Electronics

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a b s t r a c tThis paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and I on /I off characteristics. We demonstrate that a lateral strain profile corresponding to at least 0.2 eV band-gap shrinkage at the BTB source junction could act as an optimized performance Tunnel FET enabling the cancellation of the drain threshold voltage. To implement a real device, we demonstrate using GAA Si NW with asymmetric strain profile using two local stressor technologies to have >4-5 GPa peak of lateral uniaxial tensile stress in the Si NW.

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Impact of strained-silicon-on-insulator (sSOI) substrate on FinFET mobility

Cited by 71 publications

References 14 publications

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

Stress Measurements in Si and SiGe by Liquid-Immersion Raman Spectroscopy

Asymmetrically strained all-silicon multi-gate n-Tunnel FETs

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