Impact of STI on the Reliability of Narrow-Width pMOSFETs With Advanced ALD N/O Gate Stack

Penelope: The NBTI-Aware Processor

“…While increasing the length of PMOS transistors increases the degradation due to NBTI [16][17], increasing the width decreases such degradation [7]. Length is typically set to the minimum possible and only the width is changed to fit timing, power and area constraints.…”

Fuse: A Technique to Anticipate Failures due to Degradation in ALUs

“…According to our simulations and state-of-the-art measurements [10], a transistor whose width decreases by x% has a lifetime (x/5)% shorter. For instance, using a transistor in the fuse 10% narrower than its counterpart in the adder implies that its lifetime is 2% shorter.…”

“…How to weight the different factors is still an open research topic [1][2][20] [22]. However, our empirical results as well as the literature [10] show much higher dependency on the input than on the size of the transistor.…”

Effective Edge Width for 65-nm pMOSFETs and Their Variations Under CHC Stress

“…2(a) indicates that the V TH degradation in a narrowwidth device is more serious than that in the wide width. In several lectures [1]- [4], the narrow-width device under the CHC stress had more significant V TH degradation, also due to the edge-width effect. Nevertheless, the actual influence with the value of Δw is seldom mentioned.…”

“…In some lectures [1]- [4], the narrow-width device under the CHC stress proposed significant V TH degradation due to the edge-width effect. However, considering V TH degradation, these reports generally employed a schematic figure to explain the edge width contributing to the total channel width, which indirectly impacts the drain current.…”