Impact of Short-Wavelength and Long-Wavelength Line-Edge Roughness on the Variability of Ultrascaled FinFETs

Wong, Michael; Holland, Kyle D.; Anderson, S.E.; Rizwan, Shahriar; Yuan, Zhi Cheng; Hook, T.B.; Kienle, Diego; Gudem, Prasad S.; Vaidyanathan, Mani

doi:10.1109/ted.2017.2655520

Cited by 6 publications

(2 citation statements)

References 37 publications

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“…The device performance trends shown in Figures 6 and 7 seem to be well matched to the general trends, when considering several studies shown in [20][21][22][23][24][25]. Using this HS-BNN model, we can show how both the standard deviation and mean of the electrical characteristics vary with arbitrary LER profiles in various FinFET structures.…”

Section: Resultssupporting

confidence: 76%

Quantitative Evaluation of Line-Edge Roughness in Various FinFET Structures: Bayesian Neural Network With Automatic Model Selection

Baac

Son

et al. 2022

IEEE Access

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To design a device that is robust to process-induced random variation, this study proposes a machine-learning-based predictive model that can simulate the electrical characteristics of FinFETs with process-induced line-edge roughness. This model, i.e., a Bayesian neural network (BNN) model with horseshoe priors (Horseshoe-BNN), can significantly reduce the simulation time (as compared to the conventional technology computer-aided design (TCAD) simulation method) in a sufficiently accurate manner. Moreover, this model can perform autonomous model selection over the most compact layer size, which is necessary when the amount of data must be limited. The mean absolute percentage error for the mean and standard deviation of the drain-to-source current (I DS ) were ~0.5% and ~6%, respectively. By estimating the distribution of the current-voltage characteristics, the distributions of the other device metrics, such as off-state leakage current and threshold voltage, can be estimated as well.INDEX TERMS line edge roughness (LER), process-induced random variation, Bayesian neural network, automatic model selection.

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Section: Resultssupporting

confidence: 76%

Quantitative Evaluation of Line-Edge Roughness in Various FinFET Structures: Bayesian Neural Network With Automatic Model Selection

Baac

Son

et al. 2022

IEEE Access

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“…The methodology used in our analysis is an advancement over the approaches previously reported in literature, in that we simultaneously considered all the relevant sources of statistical variability, as well as their dependence on the most critical geometrical parameters. Previous works considered only Si channel material [12,[14][15][16][17][18][19][20], fewer variability sources and/or sensitivity parameters [17,[19][20][21][22][23][24], and devices not as aggressively scaled as in our investigation [12,15,17].…”

Section: Introductionmentioning

confidence: 99%

Threshold Voltage Statistical Variability and Its Sensitivity to Critical Geometrical Parameters in Ultrascaled InGaAs and Silicon FETs

Zagni

Puglisi

Verzellesi

et al. 2017

IEEE Trans. Electron Devices

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We investigate the statistical variability of the threshold voltage and its sensitivity to critical geometrical parameters in ultrascaled In0.53Ga0.47As and Si MOSFETs by means of 3-D quantum-corrected drift-diffusion simulations. Dual-gate ultrathin-body and FinFET device structures are analyzed for both channel materials. To assess the variability and sensitivity effects also from the scaling perspective, we consider devices belonging to two technological nodes with gate lengths 15 and 10.4 nm, designed according to International Technology Roadmap for Semiconductors (ITRS) specifications. Variability sources included in our analysis are random-dopant fluctuation, work-function fluctuation (WFF), as well as body- and gate-line-edge roughness (LER). Sensitivity to critical geometrical parameters is assessed by varying gate length, channel thickness, and oxide thickness. Results point out the major detrimental effect of WFF and Body-LER for InGaAs FETs, whereas WFF dominates in Si counterparts. Moreover, the sensitivity analysis shows that control over gate length and channel thickness in the InGaAs technology is fundamental in order to keep variability within tolerable values. Scaling of the InGaAs technology highlights the importance of abiding to ITRS projections regarding LER control improvement. Furthermore, a tight channel thickness control is required in ultrascaled devices due to the large sensitivity of the threshold voltage to the channel thickness combined with increased variability

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Study of Line Edge Roughness Induced Threshold Voltage Fluctuations in Double-Gate MOSFET

Sriram

Bindu

2018

2018 15th IEEE India Council International Conference (INDICON)

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Impact of Short-Wavelength and Long-Wavelength Line-Edge Roughness on the Variability of Ultrascaled FinFETs

Cited by 6 publications

References 37 publications

Quantitative Evaluation of Line-Edge Roughness in Various FinFET Structures: Bayesian Neural Network With Automatic Model Selection

Quantitative Evaluation of Line-Edge Roughness in Various FinFET Structures: Bayesian Neural Network With Automatic Model Selection

Threshold Voltage Statistical Variability and Its Sensitivity to Critical Geometrical Parameters in Ultrascaled InGaAs and Silicon FETs

Study of Line Edge Roughness Induced Threshold Voltage Fluctuations in Double-Gate MOSFET

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