Impact of Protective Layer Structures on High‐Temperature Annealing of GaN

Abstract

GaN decomposition at high‐temperature annealing after ion implantation is a huge hurdle to the further maturation of GaN technology. To solve this issue, this work studies the impact of different protective layer structures on high‐temperature annealing of GaN under 1200–1250 °C, including single‐layer structures and double‐layer structures. Single‐layer structures are the SiN layer grown by low‐pressure chemical vapor deposition (LPCVD) and the SiON layer by plasma‐enhanced chemical vapor deposition (PECVD). Double‐layer structures include oxides (Al2O3, SiO2, HfO2) deposited by atomic layer deposition (ALD) on top of low‐stress SiN by LPCVD or SiON grown by PECVD and epitaxial AlN by metal–organic chemical vapor deposition (MOCVD) with sputtered AlN. It is found that either SiO2 with the low‐stress SiN or AlN double capping layers was capable of completely preventing GaN decomposition in the temperature range of 1200–1250 °C. Finally, the protective layer with 20 nm Al2O3 and 300 nm low‐stress LP‐SiN is utilized in the annealing of Si‐implanted GaN high electron mobility transistor (HEMT) structure for activation. The excellent electrical performance are characterized. This work can provide valuable information on the ion implantation and high‐temperature annealing of GaN, which is critical for the further development of gold‐free ohmic contact with GaN devices.

Improving vertical GaN p–n diode performance with room temperature defect mitigation

“…Techniques such as multicycle rapid thermal annealing (MRTA), symmetrical MRTA, and ultrahigh-pressure annealing have been demonstrated in the literature to achieve efficient activation of dopants and restore the ion-implantationinduced crystal damage [20][21][22]. However, these processes involve multiple rapid heating and cooling cycles at high pressure in addition to conventional annealing and often require cap layers to prevent nitrogen loss in the GaN surface [23,24].…”