Impact of processing parameters on low-voltage power MOSFET threshold voltage considering defect generation

Othman, Nur Aqilah; Karim, Nissar Mohammad; Sufyan, Muhammad; Soin, Norhayati

doi:10.1109/rsm.2013.6706516

Cited by 2 publications

(3 citation statements)

References 4 publications

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“…2. VTH recovery for different recovery biases [3]. With VG_R = -2.25V a negligible recovery is shown; moving the gate bias down to -0.25 V a higher recovery occurs.…”

Section: Device Structure and Measurement Techniquementioning

confidence: 93%

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Modeling spatial and energy oxide trap distribution responsible for NBTI in p-channel power U-MOSFETs

Tallarico

Sangiorgi

Fiegna

et al. 2015

2015 IEEE 27th International Symposium on Power Semiconductor Devices &Amp; IC's (ISPSD)

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In this paper, we present a combined measurement/simulation method, implemented in order to estimate the spatial and energy oxide trap distribution induced by negative bias temperature instability (NBTI) stress in p-channel power U-MOSFETs. The methodology consists in analyzing the recovery phase at different bias conditions and correlating the results with TCAD numerical simulations. We found an oxide trap distribution positioned between 2.24 and 3.04 nm distant from oxide/channel interface with an energy level confined in the silicon bandgap

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“…2. VTH recovery for different recovery biases [3]. With VG_R = -2.25V a negligible recovery is shown; moving the gate bias down to -0.25 V a higher recovery occurs.…”

Section: Device Structure and Measurement Techniquementioning

confidence: 93%

“…Different studies have been performed on power VDMOSFETs in order to understand [2] and overcome [3] NBTI induced degradation. Recently we reported that, in power U-MOSFETs, oxide defects are the main source for the charge trapping and de-trapping occurring when NBTI stress is applied to the device [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Modeling spatial and energy oxide trap distribution responsible for NBTI in p-channel power U-MOSFETs

Tallarico

Sangiorgi

Fiegna

et al. 2015

2015 IEEE 27th International Symposium on Power Semiconductor Devices &Amp; IC's (ISPSD)

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“…There is a possibility that the defects created due to the generation of electron-hole pair might trap more electrons when a gate voltage is applied. This phenomenon increases the threshold voltage [13]. Fig.…”

Section: B Current Degradationmentioning

confidence: 93%

Threshold Voltage and Drain Current Investigation of Power MOSFET ZVN3320FTA by 2D Simulations

Kannan

Hesham

Gandhi

et al. 2019

International Journal of Simulation: Systems, Science &Amp; Technology

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Power electronic devices used in space shuttles experience degradation due to their sensitivity towards surrounding radiations. Generally, Metal-Oxide Semiconductor Field Effect Transistors (MOSFET) are used in these devices because of their fast switching speed and low power consumption capabilities. Ionizing radiation causes induced charge to build-up which damages the electrical characteristics of the MOSFET. This study investigates the threshold voltage shifts and drain current degradation for N-channel power MOSFET ZVN3320FTA by simulating experimental data on COMSOL Multiphysics. Total Ionization Dose (TID) degrade the oxide layer of MOSFETs by inducing interface-trap and oxide-trap charges. Generation of these excessive electron-hole pairs eventually causes threshold voltage shifts and current degradation.

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Impact of processing parameters on low-voltage power MOSFET threshold voltage considering defect generation

Cited by 2 publications

References 4 publications

Modeling spatial and energy oxide trap distribution responsible for NBTI in p-channel power U-MOSFETs

Modeling spatial and energy oxide trap distribution responsible for NBTI in p-channel power U-MOSFETs

Threshold Voltage and Drain Current Investigation of Power MOSFET ZVN3320FTA by 2D Simulations

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