Impact of Off-State Stress and Negative Bias Temperature Instability on Degradation of Nanoscale pMOSFET

Lee, Nam-Hyun; Kim, Hyung-wook; Kang, Bongkoo

doi:10.1109/led.2011.2174026

Cited by 22 publications

(9 citation statements)

References 9 publications

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“…The period of the stress was 1000 s (ON-state period = OFF-state period = 500 s), and the stress voltage was ¹2.8 V. This observation is similar to a previously-reported result. 4) During the OFF-state stress, I off increased due to generation of negative N ox . And during the subsequent ON-state stress, I off was decreased owing to detrapping of negative N ox and generation of positive N ox .…”

Section: Resultsmentioning

confidence: 99%

“…The reliability characteristics of pMOSFETs which operate under inverter-like conditions have been reported by few researchers. [2][3][4] The lifetime of pMOSFET under dynamic stress is longer than that of pMOSFET under the ON-state stress.…”

Section: Introductionmentioning

confidence: 99%

“…These defects influence the degradation of the subsequent ON-state stress. 4) Furthermore, as the channel width W of the pMSOFETs is scaled down, I off degradation increases dramatically due to oxide charges N ox in shallow trench isolation (STI) induced by the OFF-state stress. Eventually the degradation of I off becomes more critical than that of V th .…”

Section: Introductionmentioning

confidence: 99%

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Effect of dynamic stress on off leakage of small-dimension pMOSFETs at high temperature

Kim

Seo

Son

et al. 2014

Jpn. J. Appl. Phys.

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The degradation of the off leakage current I off in small-dimension pMOSFETs is investigated experimentally while applying a dynamic stress to the pMOSFETs. During the OFF-state stress, the dynamic stress induced an increase of I off due to generation of negative oxide charges N ox in the gate dielectric, and in the shallow trench isolation (STI) near the gate edge. When channel width W decreased, negative N ox in STI increase I off significantly, and the degradation of I off is more critical than degradation of V th. These observations indicate that the effect of the dynamic stress in pMOSFETs on I off should be seriously considered when evaluating small-dimension pMOSFETs.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Effect of dynamic stress on off leakage of small-dimension pMOSFETs at high temperature

Kim

Seo

Son

et al. 2014

Jpn. J. Appl. Phys.

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“…The gate bias is positive with respect to drain, and the high positive electric field is applied between gate and drain. As a result, negative charges are injected into the gate oxide near the drain junction by the OFF-state stress, 27) leading the decrease in «V th « (the device is strengthened) and the increase in I Dlin , 28) as shown in Fig. 1(b).…”

Section: Measurementsmentioning

confidence: 99%

Threshold voltage shifts and their variability behaviors in p-channel FETs by high voltage on-state and off-state stress

Alias

Kumar

Saraya

et al. 2014

Jpn. J. Appl. Phys.

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This paper presents threshold voltage shifts (ΔjV th j) and their variability in p-channel metal-oxide-semiconductor field effect transistors (pMOSFETs) by the high voltage ON-and OFF-state stress. Measurement data show that ΔjV th j in pFETs by the high voltage ON-and OFF-state stress depends on gate length and gate width. Larger positive ΔjV th j by the ON-state stress is obtained in shorter gate length and narrower gate width pFETs and the negative ΔjV th j by the OFF-state stress is observed only in the narrowest pFETs. It is also found that variability of ΔjV th j by the ON-state stress shows normal distribution and roughly follows the Pelgrom plot, indicating that the total trapped charges by the ON-state stress are randomly placed. These measurement data provide clear device design guidelines for the post-fabrication self-improvement scheme of static random access memory (SRAM) cell stability.

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“…Therefore, the gate bias is zero with respect to the source voltage, but the gate bias is positive with respect to the drain voltage. The stress caused by this bias condition is often called the OFF-state stress [25], [26]. Negative charges are injected into gate dielectric near drain and negative |V TH | shift (positive V TH shift) is observed.…”

Section: Measured |V Th | Shift By High Voltage Stressmentioning

confidence: 99%

Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress

Hiramoto

Kumar

Saraya

et al. 2013

IEICE Trans. Electron.

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The self-improvement of static random access memory (SRAM) cell stability by post-fabrication high-voltage stress is experimentally demonstrated and its mechanism is analyzed using 4k device-matrixarray (DMA) SRAM test element group (TEG). It is shown that the stability of unbalance cells is automatically improved by merely applying stress voltage to the V DD terminal of SRAM. It is newly found that |V TH | of the OFF-state pFETs in the SRAM cell is selectively lowered which improves the cell stability and contributes to the self-improvement.

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Impact of Off-State Stress and Negative Bias Temperature Instability on Degradation of Nanoscale pMOSFET

Cited by 22 publications

References 9 publications

Effect of dynamic stress on off leakage of small-dimension pMOSFETs at high temperature

Effect of dynamic stress on off leakage of small-dimension pMOSFETs at high temperature

Threshold voltage shifts and their variability behaviors in p-channel FETs by high voltage on-state and off-state stress

Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress

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