Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)
DOI: 10.1109/iccdcs.2000.869801
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Impact of inductance on timing characteristics of VLSI interconnects

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“…The gate of a transistor is an important delay path, because any gate resistance along with its parasitic capacitance, cause an input time-constant, consequently a delay, in the signal propagation from the input to the output. The distributed RC model, which we have employed in this work for modeling the resistance effect of the gate, is a proper model for interconnect wires [3]. The analytical models presented in this work can be useful and remedial for high performance circuits where speed is very critical.…”
Section: Introductionmentioning
confidence: 99%
“…The gate of a transistor is an important delay path, because any gate resistance along with its parasitic capacitance, cause an input time-constant, consequently a delay, in the signal propagation from the input to the output. The distributed RC model, which we have employed in this work for modeling the resistance effect of the gate, is a proper model for interconnect wires [3]. The analytical models presented in this work can be useful and remedial for high performance circuits where speed is very critical.…”
Section: Introductionmentioning
confidence: 99%