Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

Salas-Villasenor, A. L.; Mejía, I.; Hovarth, J.; Alshareef, Husam N.; K., D.; Ramı́rez-Bon, R.; Gnade, Bruce E.; Quevedo‐Lopez, Manuel

doi:10.1149/1.3456551

Cited by 40 publications

(32 citation statements)

References 37 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In recent papers, we found that ammonia-free chemically deposited CdS layers perform quite well as window layers in CdTe/CdS solar cells and as semiconductor active layers in thin film transistors [11][12][13]. PbS is another absorbent material that can be coupled with CdS layers in solar cells.…”

Section: Introductionmentioning

confidence: 99%

Thin film solar cells of CdS/PbS chemically deposited by an ammonia-free process

Hernández-Borja

Vorobiev

Ramı́rez-Bon

2011

Solar Energy Materials and Solar Cells

140

View full text Add to dashboard Cite

Section: Introductionmentioning

confidence: 99%

Thin film solar cells of CdS/PbS chemically deposited by an ammonia-free process

Hernández-Borja

Vorobiev

Ramı́rez-Bon

2011

Solar Energy Materials and Solar Cells

140

View full text Add to dashboard Cite

“…Then, 90 nm of HfO 2 is deposited using atomic layer deposition (ALD) at 100°C to serve as gate dielectric. After the gate dielectric formation, the substrates were immersed in a chemical bath using an ammonia-free solution to deposit 70 nm CdS films at 70°C on top of the HfO 2 [22]. Afterwards, 500 nm of parylene-C was deposited immediately on top of CdS to act as a protective film to prevent any of the chemicals commonly used in photolithography touching the CdS.…”

Section: Cds Tftmentioning

confidence: 99%

CdS Thin Film Transistor for Inverter and Operational Amplifier Circuit Applications

Wondmagegn

Mejía

Salas-Villasenor

et al. 2016

Microelectronic Engineering

Self Cite

View full text Add to dashboard Cite

Organic and inorganic thin film transistors (TFTs) are fabricated, simulated, and tested for circuit applications. The devices are based on polycrystalline cadmium sulfide (CdS) and pentacene thin films. Both devices are simulated and analyzed using two-dimensional finite element simulation methodology. For CdS, grain boundary and uniform trap distribution approaches are implemented. It is assumed that traps due to grain boundaries are uniformly distributed throughout the film. For pentacene a Poole-Frenkel mobility model is employed. After matching device simulation with experimental data, the SPICE model parameters are extracted for circuit simulation. The devices are tested for both analog and digital circuits. operational amplifier (OPAMP) and inverter circuits are tested. Two OPAMP topologies are compared and the results are discussed. One of the topologies is based on all n-type transistors using CdS TFT and the other topology is the two-stage Miller compensated CMOS design based on CdS and pentacene TFTs. The operational amplifiers have an open-loop voltage gain of 25.9 dB and 29.7 dB respectively. The performance of the CMOS design is found to be limited by performance of pentacene transistor.

show abstract

“…R ECENTLY, the deposition of solution-based materials has attracted a lot of attention due to its potential use in low-cost methods to fabricate thin-film transistors (TFTs) [1]- [5] and circuits [6]- [22] for flexible and large area electronics. One particular technique that has attracted the attention of many researchers is inkjet printing.…”

Section: Introductionmentioning

confidence: 99%

Enabling Hybrid Complementary-TFTs With Inkjet Printed TIPS-Pentacene and Chemical Bath Deposited CdS

Mejía

Perez

Kabir

et al. 2014

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

We report the fabrication and device analysis to enable high performance/low-temperature complementary thinfilm transistors (CTFTs) with 6, 13-Bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) and cadmium sulfide (CdS). Isolated transistors are first studied and then integrated in a fully patterned CTFT structure. N-type TFTs were fabricated using atomic layer deposition HfO 2 as gate dielectric, followed by a CdS film deposited by chemical bath deposition at 70°C. A novel approach that uses a parylene-C hard mask to avoid damage to the CdS n-type semiconductor is introduced. Also, a comparison between the n-type transistor performance using two different metals (Au and Al) for source-drain electrodes is presented. P-type transistors were fabricated using a novel approach that combines photolithography and ink-jet printing processes. TIPS-pentacene is deposited with inkjet printing in the active channel well, which is photolithographically defined. The p-type TFT mobilities ranged from 1.2 × 10 −3 to 1.5 × 10 −2 cm 2 /V-s, whereas for n-type TFTs mobilities were ∼10 cm 2 /V-s. CTFTs with a maximum processing temperature of 150°C are demonstrated. Inverters with gains of 17 were achieved. This fabrication process is compatible with large area and low-cost technologies for flexible electronics applications.

show abstract

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

Cited by 40 publications

References 37 publications

Thin film solar cells of CdS/PbS chemically deposited by an ammonia-free process

Thin film solar cells of CdS/PbS chemically deposited by an ammonia-free process

CdS Thin Film Transistor for Inverter and Operational Amplifier Circuit Applications

Enabling Hybrid Complementary-TFTs With Inkjet Printed TIPS-Pentacene and Chemical Bath Deposited CdS

Contact Info

Product

Resources

About