Impact of Forward Body-Biasing on Ultra-Low Voltage Switched-Capacitor RF Power Amplifier in 28 nm FD-SOI

Tochou, Guillaume; Cathelin, Andreia; Frappé, Antoine; Rabaey, Jan M.

doi:10.1109/tcsii.2021.3088996

Cited by 5 publications

(3 citation statements)

References 18 publications

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“…The technology constant µn and Cox is the mobility of charge and capacitance of gate oxide, respectively, W/L is the ratio of channel width over length, and VGS-VTH is the overdrive voltage. Body-biasing techniques are widely employed to scale the threshold voltage dynamically, VTH [34], [35] to minimize conduction loss at low-voltage applications.…”

Section: ) Conduction Lossmentioning

confidence: 99%

Design and Implementation of Hybrid DC-DC Converter: A Review

et al. 2023

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The advancement in Power Management Integrated Circuit (PMIC) has driven the DC-DC conversion technology into a System-on-Chip (SoC) solutions, leveraging CMOS technology scaling from 180nm to 22nm and on-chip passive element integration. Concurrently, as the applications demand smaller form factor solution towards device portability with optimized power qualities, switched-capacitor-inductor hybrid architectures with fully-integrated passives have become a popular choice for a compact and high efficiency converter solution, in contrast to bulky and discrete component based alternatives. This article reviews the latest advancements in hybrid dc-dc topologies, specifically for low-power applications to address the downsides such as charge sharing loss, high current ripple, limited conversion ratio, low power density and efficiency. An overview of capacitor and inductor technology is discussed in terms of on-chip parasitic losses, and miniaturization. A comprehensive comparison in the state-of-the-art hybrid dc-dc converter work is tabulated with power density and efficiency as the primary performance metrics, highlighting their operability in low-power applications. Moreover, a discussion is included with quantified benchmarks to justify the viability of converters, along with the future recommendation of realizing ultra-high switching frequency for smaller footprint inductor and design approach to resolve the current tradeoff bottlenecks.

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Section: ) Conduction Lossmentioning

confidence: 99%

Design and Implementation of Hybrid DC-DC Converter: A Review

et al. 2023

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“…The forward body-biasing (FBB) knob, specific to FD-SOI technologies, is used to lower the threshold voltage of the transistors, reducing r on at the low 0.5 V supply voltage, limiting their size and parasitic capacitance which improves the efficiency of the power amplifier as well as saving area. By using the simulation-validated model proposed in [39] it is shown in Figure 10 that a forward body-biased SCPA improves by 6 % the peak system efficiency (SE peak ) of the power amplifier while reducing by 45 % the switches area at 450 MHz. For further area saving the unit capacitances C u in each slice are MOM capacitances stacked on top of the inverters.…”

Section: B Edge-combiners Switched-capacitor Power Amplifiermentioning

confidence: 99%

A Sub-100-μW 0.1-to-27-Mb/s Pulse-Based Digital Transmitter for the Human Intranet in 28-nm FD-SOI CMOS

Tochou

Benarrouch

Gaidioz

et al. 2022

IEEE J. Solid-State Circuits

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Human body communications require energyefficient transceivers to connect diverse devices on the human body for wellness and medical applications. This paper presents a fully digital pulse-based transmitter (TX) for capacitive bodycoupled communications (c-BCC) in 28 nm FD-SOI CMOS. The transmitter is operating at 450 MHz where surface wave (SW) propagation is the dominant mechanism of capacitive body coupled communication (c-BCC), offering a larger bandwidth with a more stable channel. The heavily duty-cycled transmitter uses a 90 MHz free-running oscillator and edge combiners to generate OOK Gaussian-shaped pulses through a switchedcapacitor PA. Wide range forward body-biasing (FBB), specific to FD-SOI technology, allows frequency tuning and adaptive efficiency optimization as a function of data rate. The proposed transmitter consumes 17 to 76 µW for flexible data rates from 0.1 to 27 Mb/s (170 pJ/b down to 2.8 pJ/b) with up to 14 % system efficiency under 0.5 V supply voltage.

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“…Rail-to-rail tapered buffers are extensively applied as gate drivers in a variety of switching-mode circuits such as power amplifiers (PAs) [1][2][3] [4], and DC-DC converters [5][6] [7] [8]. While tapered buffers in digital applications emphasize energy and delay [9] [10], gate drivers focus on the energy dissipation for a given drive capability.…”

Section: Introductionmentioning

confidence: 99%

Computer-aided Design of Cross-voltage-domain Energy-optimized Tapered Buffers

CAO,

HAN,

LYU

2024

IEICE Trans. Electron.

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This paper introduces a computer-aided low-power design method for tapered buffers that address given load capacitances, output transition times, and source impedances. Cross-voltage-domain tapered buffers involving a low-voltage domain in the frontier stages and a highvoltage domain in the posterior stages are further discussed which breaks the trade-off between the energy dissipation and the driving capability in conventional designs. As an essential circuit block, a dedicated analytical model for the level-shifter is proposed. The energy-optimized tapered buffer design is verified for different source and load conditions in a 180-nm CMOS process. The single-𝑉 𝐷𝐷 buffer model achieves an average inaccuracy of 8.65% on the transition loss compared with Spice simulation results. Crossvoltage tapered buffers can be optimized to further remarkably reduce the energy consumption. The study finds wide applications in energy-efficient switching-mode analog applications.

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Impact of Forward Body-Biasing on Ultra-Low Voltage Switched-Capacitor RF Power Amplifier in 28 nm FD-SOI

Cited by 5 publications

References 18 publications

Design and Implementation of Hybrid DC-DC Converter: A Review

Design and Implementation of Hybrid DC-DC Converter: A Review

A Sub-100-μW 0.1-to-27-Mb/s Pulse-Based Digital Transmitter for the Human Intranet in 28-nm FD-SOI CMOS

Computer-aided Design of Cross-voltage-domain Energy-optimized Tapered Buffers

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