Impact of dimensional scaling and size effects on beyond CMOS All-Spin Logic interconnects

Abstract

The energy-per-bit and delay of All-Spin Logic (ASL) interconnects have been modeled. Both Al and Cu interconnect channels have been considered and the impact of size effects and dimensional scaling on their potential performance has been quantified. It is predicted that size effects will affect ASL interconnects more severely than electrical interconnects.

Smart Detector Cell: A Scalable All-Spin Circuit for Low Power Non-Boolean Pattern Recognition

“…As shown in the Fig. 1(b-d) and discussed in [18], the applied voltage on the input ferromagnet, creates a flow of electrons which moves them from the supply voltage to the ground. This flow of electrons, becomes spin-polarized when passing through the input ferromagnet.…”

“…The accurate parameters of channel, magnet and interface that determine different performance characteristics, e.g., the spin injection, detection and transport efficiency are taken into account. The main important size effect parameters for the purpose of this work are the side wall specularity, the grain boundary reflectivity and the average grain size [18]. The average grain size is assumed to be equal to the width of thickness of the metals [18].…”

“…The main important size effect parameters for the purpose of this work are the side wall specularity, the grain boundary reflectivity and the average grain size [18]. The average grain size is assumed to be equal to the width of thickness of the metals [18]. The complete list of parameters is in Appendix B.…”