Impact of Deep Sub-Micron Design Rules on Optimization of RESURF LDMOSFETs

Abstract

In this paper we demonstrate and evaluate the impact of deep sub-micron design rules on the performance of RESURF LDMOSFET devices in smart power technologies. It is observed that the device parameters such as breakdown voltage, specific onresistance, safe operating area (SOA) depend significantly on the width of the drain active opening. Simply reducing the active opening width to minimum allowed by the technology design rules may not always yield best device performance. In deep sub-micron smart power technologies where one or two implants are often utilized to construct variety of devices for multiple voltage-tiers, this can provide an effective tool for device performance optimization.