Impact of charging on breakdown in deep trench isolation structures [parasitic MOSFET example]

Elattari, B.; bosch, G. Van den; Schoenmaker, Wim; Groeseneken, G.; Coppens, P.; Moens, P.; Pestel, F. De

doi:10.1109/essderc.2003.1256926

Cited by 5 publications

(2 citation statements)

References 3 publications

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“…The following are the three requirements for isolation devices: compactness, energy saving and low cost. On-chip isolation technology is one of the most adequate approaches for realizing these requirements [15][16][17] and several on-chip isolation devices with a multi trench isolation structure have been reported. [18][19][20][21][22][23][24][25] Figure 2 shows a review status of multi trench gap isolation structures.…”

Section: Introductionmentioning

confidence: 99%

Analysis and reduction of leakage current of 2 kV monolithic isolator with wide trench spiral isolation structure

Takeuchi¹,

Kuroda²,

Sugawa³

2016

Jpn. J. Appl. Phys.

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In this work, the origin of the leakage current of a highly area-efficient silicon-on-insulator (SOI) monolithic isolator using a spiral trench isolation structure is clarified by experimental and simulation analyses and its reduction method is proposed. It was found that parasitic MOSFET inversion and accumulation channels formed at the SOI and buried oxide (BOX) interface are the origins of leakage current. To reduce the leakage current, adequate SOI spiral length and width and BOX layer thickness are proposed for various voltage usages and show the possibility of 4 kV voltage tolerance and 500 MΩ isolation resistivity.

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Section: Introductionmentioning

confidence: 99%

Analysis and reduction of leakage current of 2 kV monolithic isolator with wide trench spiral isolation structure

Takeuchi¹,

Kuroda²,

Sugawa³

2016

Jpn. J. Appl. Phys.

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“…There are many examples reported about DTI. [8][9][10][11][12][13][14][15][16][17]28) SOI technology is also shown to be effective for isolation in the vertical direction. [18][19][20][21][22][23][24][25][26][27] In this work, we introduce the unified impedance model to analyze the breakdown voltage of various isolation structures.…”

Section: Introductionmentioning

confidence: 99%

Analysis of breakdown voltage of area surrounded by multiple trench gaps in 4 kV monolithic isolator for communication network interface

Takeuchi¹,

Kuroda²,

Sugawa³

2015

Jpn. J. Appl. Phys.

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We analyzed the shared voltages of multiple trench gaps on a silicon-on-insulator (SOI) substrate and showed the conditions for improving the breakdown voltage surrounded by these isolated structures. We introduced a unified impedance model instead of the capacitive model of trench gaps and determined the effective conditions for improving the breakdown voltage. The first condition is to reduce the impedance of trench gaps. In this case, the leak current gives a low limit of trench gap resistance. The second condition is to increase the substrate resistance. As silicon substrate resistance is not very high, this condition is not useful for the silicon substrate, but for other materials such as ceramics. We confirmed the effectiveness of these conditions from the simulation and experimental results of a fabricated chip.

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Breakdown and hot carrier injection in deep trench isolation structures

Elattari

Coppens

bosch

et al. 2005

Solid-State Electronics

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Impact of charging on breakdown in deep trench isolation structures [parasitic MOSFET example]

Cited by 5 publications

References 3 publications

Analysis and reduction of leakage current of 2 kV monolithic isolator with wide trench spiral isolation structure

Analysis and reduction of leakage current of 2 kV monolithic isolator with wide trench spiral isolation structure

Analysis of breakdown voltage of area surrounded by multiple trench gaps in 4 kV monolithic isolator for communication network interface

Breakdown and hot carrier injection in deep trench isolation structures

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