Impact of Charge-Trap Layer Conductivity Control on Device Performances of Top-Gate Memory Thin-Film Transistors Using IGZO Channel and ZnO Charge-Trap Layer

Improvement in Mechanical Durability of Stretchable Charge-Trap Memory Transistors with Engineered Wavy-Dimensional Structures

“…While there was no marked hysteresis in transfer curves for the IGZO TFTs, an MW as wide as 23.8 V was obtained for the CTM-TFTs. These results clearly demonstrate that the V th shift obtained in the CTM-TFT originated from the charge-trap/detrap events rather than unstable charge injection caused by interface defect sites. ,, …”

“…These results clearly demonstrate that the V th shift obtained in the CTM-TFT originated from the charge-trap/detrap events rather than unstable charge injection caused by interface defect sites. 15,16,34 For further investigations on memory operations, the transfer curves were measured at various V GS sweep ranges of ±10, ± 15, and ±20 V, as shown in Figure 2c. The chargetrap-assisted MW could be clearly obtained even at ±10 V. The MW values monotonously increased with the amplitude of program voltages, reflecting the fact that the concentration of trapped electrons can be controlled during the program operations.…”

Amorphous InGaZnO (a-IGZO) Synaptic Transistor for Neuromorphic Computing

“…Not only trap characteristics but also the conductivity of CTL must be controlled. In the case of ZnO, which is CTL mostly deposited by ALD for IGZO-based memory and synaptic transistors, a high deposition temperature must be avoided because of its higher conductivity …”

“…In the case of ZnO, which is CTL mostly deposited by ALD for IGZO-based memory and synaptic transistors, a high deposition temperature must be avoided because of its higher conductivity. 140 To the best of our knowledge, CTL-type IGZO synaptic transistor using photonic stimulation has yet to be investigated. However, the recent study of CTL-type (Al 2 O 3 /ZrO 2 /Al 2 O 3 ) MoS 2 optoelectronic synaptic transistor achieved 18.3 aJ per electrical spike (−4 V, d t = 100 ns) and emulated learningforgetting-relearning behavior by photonic spikes (λ = 350 nm).…”

Synergic Impacts of CF4 Plasma Treatment and Post-thermal Annealing on the Nonvolatile Memory Performance of Charge-Trap-Assisted Memory Thin-Film Transistors Using Al–HfO2 Charge Trap and In–Ga–Zn–O Active Channel Layers

“…Amorphous oxide semiconductors (AOSs) have been attracting much attention as active layers to replace polycrystalline silicon channels for advanced three-dimensional device structures due to various advantages such as high mobility, low-temperature compatibility, and grain-boundary-free uniform natures. − Alternatively, charge-trap-assisted memory thin-film transistors (CTM-TFTs) utilizing AOS channels, in which the charges are stored in localized trap sites within the charge-trap layers (CTLs), can be promising candidates as next-generation nonvolatile memories (NVMs), which are featured to have such advantages as a low operating voltage, excellent operational reliabilities, and compatibility with complementary metal oxide semiconductor technology (CMOS). − With the aim of realizing highly functional nonvolatile CTM-TFTs, various strategies, such as the introduction of high-dielectric-constant (high-k) CTLs, − CTL engineering, − and interfacial treatments between the tunneling layer (TL) and CTL, − have been investigated in order to enhance the program/erase (P/E) efficiencies and NVM reliabilities with improving the CTL trap densities and interfacial qualities. Alternatively, the continuous device scaling urges to further reduce the physical thickness of the gate stacks including the CTL and TL, and hence, the conventional CTM devices employing silicon nitride (Si 3 N 4 ) CTLs have faced the critical limit of a trade-off relationship between P/E speed and memory retention time. , Therefore, to overcome this problem and enhance the memory characteristics in terms of charge-trapping efficiency and equivalent oxide thickness (EOT) scaling, we previously demonstrated the NVM characteristics assisted by charge-trap/detrap events of the CTM-TFTs using oxide semiconductor materials, such as ZnO, − ,− In–Ga–Zn–O, (IGZO), and Hf-doped ZnO, as CTLs. Irrespective of successful demonstrations on previously reported CTM-TFTs employing the oxide channel, the choice of oxide semiconductor CTLs needed to be patterned with a double-layered tunneling oxide to avoid chemical damages induced into the channel layer during the patterning process .…”