Impact of cell distance and well-contact density on neutron-induced Multiple Cell Upsets

Furuta, Jun; Kobayashi, Kazutoshi; Onodera, Hidetoshi

doi:10.1109/irps.2013.6532053

Cited by 25 publications

(2 citation statements)

References 14 publications

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“…To measure SEU rates on FFs, we prepare an FF array on the basis of a shift register, which is constructed using FFs and a clock buffer chain. 23,24) Figure 6 shows the schematic of the FF array and Fig. 7 shows that of the implemented FF.…”

Section: Ff Array For Measuring Seu Ratesmentioning

confidence: 99%

Radiation hardness evaluations of 65 nm fully depleted silicon on insulator and bulk processes by measuring single event transient pulse widths and single event upset rates

Furuta

Sonezaki²,

Kobayashi³

2015

Jpn. J. Appl. Phys.

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We measure single event transient (SET) pulse widths on inverter chains and single event upset (SEU) rates on flip-flops (FFs) fabricated in 65 nm fully depleted silicon on insulator (FD-SOI) and bulk processes. The layout designs of test chips are strictly identical between their processes besides buried oxide (BOX) layers. Experimental results show that neutron-induced SEU and SET rates in the FD-SOI process are 230' and 450' lower than those in the bulk process, respectively.

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Section: Ff Array For Measuring Seu Ratesmentioning

confidence: 99%

Radiation hardness evaluations of 65 nm fully depleted silicon on insulator and bulk processes by measuring single event transient pulse widths and single event upset rates

Furuta

Sonezaki²,

Kobayashi³

2015

Jpn. J. Appl. Phys.

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“…Scrubbing technique used to reprogram an FPGA. It is a slow serial process going through every memory word looking for errors to repair [17]. The two types of errors are hard and soft error.…”

Section: Introductionmentioning

confidence: 99%

Multi-Bit Error Resilient FPGA Cram with Minimum TTD

B. Kala,

D. Arulanantham

2024

Int Res J Adv Engg Hub

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In harsh environments such as space, radiation and charged particles cause Single-Event and Multi-bit Effects, faults occurring randomly on any electronic component. These must be mitigated to ensure device functionality. Modern mitigation methods, such as triple modular redundancy, are very effective against Single Event Transients (SETs), but incur a minimum of 3× cost in area. Single-Event Upsets (SEUs) affect sequential elements and are regularly repaired using memory scrubbing. Scrubbing is a slow serial process, going through every memory word looking for errors to repair. It involves a non-negligible Time to Detect (TTD) before repair, during which other events can occur and compromise the system. Field Programmable Gate Arrays (FPGAs) rely heavily on sequential elements to store their configuration; thus, FPGA’s SEU detection time is critical to ensuring design integrity in harsh conditions. It is required a robust error correction code (ECC) to protect electronic devices from MCUs. The proposed work describes the conception, implementation and evaluation of new algorithm using matrix code for the detection and correction of multiple errors in FPGA configuration memories. The combined architecture with multiple bit segment with parity bits helps in locating and correcting double-triple bit errors. The proposed Method allows asynchronous MEU detection and replaces scrubbing variable time to detect with a fixed TTD. The IMECCC based on Matrix code reduces FPGA’s TTD compared to existing method.

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Radiation-Induced Soft Errors

Ibe¹,

Yoshimoto

et al. 2018

VLSI Design and Test for Systems Dependability

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Impact of cell distance and well-contact density on neutron-induced Multiple Cell Upsets

Cited by 25 publications

References 14 publications

Radiation hardness evaluations of 65 nm fully depleted silicon on insulator and bulk processes by measuring single event transient pulse widths and single event upset rates

Radiation hardness evaluations of 65 nm fully depleted silicon on insulator and bulk processes by measuring single event transient pulse widths and single event upset rates

Multi-Bit Error Resilient FPGA Cram with Minimum TTD

Radiation-Induced Soft Errors

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