Impact of Aspect Ratio and Interface Trap Charge on the Performances of Junctionless MOSFET-Based Adiabatic Logic Circuit

Ganguli, Tanushree; Chanda, Manash; Sarkar, Angsuman

doi:10.1109/ted.2023.3327348

Cited by 2 publications

(1 citation statement)

References 26 publications

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“…Recently, owing to their improved performance in semiconductor substances, metal-(insulator/oxide/ polymer-semiconductor/ferroelectric)-semiconductor (MIS/MOS/MPS/MFS) structures have gained increasing attention [1][2][3][4][5]. These architectures are commonly employed in various electronic/optoelectronic applications, including sensors, phototransistors, solar cells, light-emitting diodes, logic circuits, and microwave rectifiers [6][7][8][9][10][11][12]. The insertion of a thin layer at the metal/semiconductor (M/S) surface hinders the transport of charge carriers between them, altering the conduction process/mechanisms (CPs/CMs).…”

Section: Introductionmentioning

confidence: 99%

Enhanced electrical parameters of the Au/n-Si Schottky barrier diodes with graphite/graphane oxide doped PVC interlayer

Taşçıoğlu,

Badali,

Altındal Yerişkin

2024

Phys. Scr.

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In this work, Schottky diodes (SDs) formed on n-Si substrates were created using polyvinyl-chloride (PVC) and graphite/graphene-oxide (Gt/GO) nanoparticles (NPs) doped PVC interlayers and the conduction mechanisms of the structures were compared to the reference Au/n-Si (MS) diode. The characterization methods, including XRD, FE-SEM, and EDX, are used to analyze Gt/GO NPs and examine their structural, morphological, and analytical properties. In addition to the standard I-V method, modified Norde and Cheung methods were applied to analyze the forward bias I-V characteristics to determine the impact of pure-PVC and (PVC: Gt-GO) interlayers' main electronic parameters on the SDs. The surface state density (Dit) depending on energy was also determined from the forward bias current-voltage by considering the voltage-dependent ideality coefficient, n(V), and barrier height, ΦB(V). The outcomes showed that, as compared to MS structures, both the pure-PVC and (PVC: Gt-GO) interlayer leads to a decrease of n, leakage-current, Dit, an increase of rectification ratio (RR), shunt-resistance (Rsh) and zero-bias barrier-height (ΦB0). The differences in the electronic parameters observed between the I-V, Norde, and Cheung functions indicate that these parameters are highly reliant on the voltage and the computation method utilized. The barrier inhomogeneities at the metal/semiconductor surface also affect the current-transport or conduction mechanisms.

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