Impact of analog IC impairments in SiPM interface electronics

Abstract

The recent realization of Silicon Photomultiplier (SiPM) devices as solid-state detectors for Positron Emission Tomography holds the promise of improving image resolution, integrating a significant portion of the interface electronics, and potentially lowering the power consumption. Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing and is currently working on taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. To date, relatively little modeling has been done to understand the impact of analog non-idealities associated with the front-end electronics, on SiPM-based PET systems. This paper focuses on various analog impairments associated with PET scanner readout electronics. Matlab was used as a simulation platform to model the noise, linearity and signal bandwidth of the frontend electronics with the measured SiPM pulses as the input.

A CMOS front-end interface ASIC for SiPM-based positron emission tomography imaging systems

“…R1 and C1 compensate the frequency response of the loop with a zero, maintaining loop stability. The CG stage introduces noise at higher frequencies, but a signal-to-noise ratio of 5 dB at the output of the interface electronics is enough to maintain the full width at half maximum (FWHM) energy resolution of the SiPM pulses [8]. As a result, relatively modest noise performance is required of the front-end interface electronics in a SiPM based PET Imaging System.…”