Impact of aggressive fin width scaling on FinFET device characteristics

He, Xiaoli; Fronheiser, Jody; Zhao, Pei; Hu, Zhanyuan; Uppal, S.; Wu, Xusheng; Hu, Yue; Sporer, R.; Qin, Lu; Krishnan, R.; Bazizi, El Mehdi; Carter, R.; Tabakman, K.; Jha, Ashish Kumar; Hónɡ, Yú; Hu, Owen; Choi, Dae Ro; Lee, J. G.; Samavedam, Srikanth; Sohn, Dong Kyun

doi:10.1109/iedm.2017.8268427

Cited by 34 publications

(20 citation statements)

References 1 publication

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“…Fin field effect transistor (FinFET) technology is the leading architecture for high performance (HP) applications. However, FinFETs will struggle to keep control of device electrostatics in future generations of complementary metaloxide-semiconductor (CMOS) technology [1]. The eventual changeover to different architectures like nanosheet (NS) [2]- [5] or nanowire (NW) FETs [6], [7], and/or to different channel materials like Ge or III-Vs [8]- [10] requires thorough ground work.…”

Section: Introductionmentioning

confidence: 99%

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

et al. 2020

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Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length (L G) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to L G of 16 nm offering a larger on-current (I ON) and slightly better sub-threshold characteristics. Below L G of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current (I OFF), and the largest I ON /I OFF ratio out of the three architectures. However, the NW FET suffers from early I ON saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body.

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Section: Introductionmentioning

confidence: 99%

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

et al. 2020

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“…As a result, ambipolar current reduces. 4.6 Transconductance(g m ),Transconductance generation e ciency(TGF) and Total Gate Capacitance(C gg )…”

Section: Ambipolairtymentioning

confidence: 99%

“…Nanosheets have emerged as a potential successor to conventional Finfets and stacked nanowires for 7nm technology and beyond [1][2][3]. Finfets need tall and thin ns, which enhance the fabrication cost and complexity [4] while the surface roughness factor degrades the performance of stacked nanowires [5]. The Nanosheet Field Effect Transistor (NS-FET) exhibits enormous current density due to its increased effective width per footprint [6].…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

Jain

Sawhney

Kumar

et al. 2021

Silicon

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In this paper, a novel vertically stacked silicon Nanosheet Tunnel Field Effect Transistor (NS-TFET) device scaled to a gate length of 12nm with Contact poly pitch (CPP) of 48nm is simulated. NS-TFET device is investigated for its electrostatics characteristics using technology computer-aided design (TCAD) simulator. The inter-band tunneling mechanism with a P-I-N layout has been incorporated in the stacked nanosheet devices. The asymmetric design technique for doping has been used for optimum results. NS-TFET provides a low leakage current of order10 -16 A, an excellent subthreshold swing (SW) of 23mv/decade, and negligible drain induced barrier lowering (DIBL) having a value of 10.5 mv/V. The notable ON to OFF current ratio of the order of 10 11 has been achieved. The device exhibits a high transconductance of 3.022x10 -5 S at the gate to source voltage of 1V. NS-TFET shows tremendous improvement in short channel effects (SCE) and is a good option for advanced technologies.

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“…As a result, vertically stacked Si-Gate-All-Around (GAA) nanosheet FETs (NSFETs) were proposed as a promising candidate to replace Si-FinFETs due to those superior electrostatics below 7-nm node [11]- [14]. But both Si-FinFETs and Si-NSFETs have inevitable parasitic channels below the intrinsic channels that critically affect the leakage current, which is the killing factor of scaled transistors [15], [16]. Especially, the Si-NSFETs are deeply concerned because of wider parasitic channels than the Si-FinFETs.…”

Section: Introductionmentioning

confidence: 99%

Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application

et al. 2020

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Excess source and drain (S/D) recess depth (T SD) variations were analyzed comprehensively as one of the most critical factors to DC/AC performances of sub 5-nm node Si-Nanosheet (NS) FETs for system-on-chip (SoC) applications. Variations of off-, on-state currents (I off , I on) in three-stacked NS channels and parasitic bottom transistor (tr pbt), gate capacitance (C gg), intrinsic switching delay time (τ d), and static power dissipation (P static) are investigated quantitatively according to the T SD variations. More S/D dopants diffuse into the tr pbt with the deeper T SD , so the I off and I on increase due to raised current flowing through the tr pbt. Especially, the I off of PFETs remarkably increases above the certain T SD (T SD,critical) compared to NFETs. Furthermore, the I on contribution of each channels having the T SD,critical is the largest at the top NS channel and the tr pbt has the ignorable I on contribution. Among the NS channels, the top (bottom) NS channel has the largest (smallest) I on contribution due to its larger (smaller) carrier density and velocity for both P-/NFETs. The C gg also increases with the deeper T SD by increasing parasitic capacitance, but fortunately, the τ d decreases simultaneously due to the larger increasing rate of the I on than that of the C gg for all SoC applications. However, the P static enormously increases with the deeper T SD , and low power application is the most sensitive to the T SD variations among the SoC applications. Comprehensive analysis of the inevitable tr pbt effects on DC/AC performances is one of the most critical indicators whether Si-NSFETs could be adopted to the sub 5-nm node CMOS technology.

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Impact of aggressive fin width scaling on FinFET device characteristics

Cited by 34 publications

References 1 publication

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application

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