Impact ionization measurements and modeling for power PHEMT

Abstract

A systematic study of impact ionization in pseudomorphic high electron mobility transistors (PHEMTs) has been carried out using temperature-dependent electrical measurements as well as modeling for optimizing the power performance of the devices through the best layout parameters. A measurement procedure makes it possible to define a safe transistor operation region is proposed. Impact ionization in the channel is parameterized by specific gate current and voltage values. Temperature-dependent measurements are shown to provide distinction between the impact ionization current and the thermionic field emission current. A methodology for defining an optimum vertical structure and a lateral layout for a given application and operational conditions is developed. Empirical models for optimum lateral layout for a power application were developed based on a statistical "Device Zoo" approach. The results point to an optimal gate-to-drain distance for minimum impact ionization current.Index Terms-Breakdown, empirical models, impact ionization, pseudomorphic high electron mobility transistors (PHEMT).

Examination of hot carrier effects of the AlGaAs/InGaAs pHEMT through device simulation

“…While the stress mechanisms are known [2][3][4][5][6][7][8][9][10], this work provides a concise display of impact ionization, hole and electron current and ambient temperature under various types of stress regimes.…”

“…Consequently, an increase of selfheating through current conduction helps decrease impact ionization [10].…”

“…The reliability of the pHEMT is a subject matter that has been studied by several authors, [2][3][4][5][6][7][8][9][10] and continues to be important due to the high demands of military and commercial applications for continuous low power consumption, high efficiency and superb performance. It is therefore important to understand the physical mechanisms involved behind the reliability of pHEMT devices.…”

Performance stability of AlGaN/GaN HFET: effect of plasma processing

“…All transfer characteristics were measured at 15 V of V D , while V GS was swept from -8 V to 2 V. Electrical stress in impact ionization (II) region was performed for devices with and without plasma treatment. The impact ionization region was defined by a characteristic gate current "hump" [6,7]. The conditions were 80 V of V D , 200 sec of stress duration.…”

Performance characterization of III–V power devices

“…The two-level device matrix makes it possible to model the electrical characteristics of the matrix taking into account the entire first and second order effects. Without loss of generality [11,12], the following ranges of five key layout parameters have been chosen in our case to optimize a 10 GHz HPA: L g -0.2-0.3 lm, L wr -1.4-1.7 lm, L ds -3-3.5 lm, L wr,g -0.4-0.6 lm and L s,wr -0.7-0.9 lm.…”