IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm<sup>2</sup> CIM-SRAM With Multi-Bit Analog Batch-Normalization

Kneip, Adrian; Lefebvre, Martin; Verecken, Julien; Bol, David

doi:10.1109/jssc.2023.3269098

Cited by 8 publications

(1 citation statement)

References 25 publications

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“…If these cooling requirements can be removed, these techniques could become very lucrative for future high-performance mobile computing systems, but there is still much research needed to reach that goal. [1,[14][15][16]82], Adiabatic [53,62], Alternative [55,81,83,84], Analog [31,75,[85][86][87][88][89], IMC [40,61,79,90,91]).…”

Section: Discussion and Future Directionsmentioning

confidence: 99%

Survey of Novel Architectures for Energy Efficient High-Performance Mobile Computing Platforms

O’Connor,

Elfouly,

Alouani

2023

Energies

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There are many real-world applications that require high-performance mobile computing systems for onboard, real-time processing of gathered data due to latency, reliability, security, or other application constraints. Unfortunately, most existing high-performance mobile computing systems require a prohibitively high power consumption in the face of the limited power available from the batteries typically used in these applications. For high-performance mobile computing to be practical, alternative hardware designs are needed to increase the computing performance while minimizing the required power consumption. This article surveys the state-of-the-art in high-efficiency, high-performance onboard mobile computing, focusing on the latest developments. It was found that more research is needed to design high-performance mobile computing systems while minimizing the required power consumption to meet the needs of these applications.

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Section: Discussion and Future Directionsmentioning

confidence: 99%

Survey of Novel Architectures for Energy Efficient High-Performance Mobile Computing Platforms

O’Connor,

Elfouly,

Alouani

2023

Energies

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Dual in-memory computing of matrix-vector multiplication for accelerating neural networks

Wang,

Sun

2024

Device

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The Multilayer Neural Network Implementation Using SRAM-Based Reconfigurable Cognitive Computation Matrices

Liu,

Chen,

et al. 2024

2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS)

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IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm² CIM-SRAM With Multi-Bit Analog Batch-Normalization

Cited by 8 publications

References 25 publications

Survey of Novel Architectures for Energy Efficient High-Performance Mobile Computing Platforms

Survey of Novel Architectures for Energy Efficient High-Performance Mobile Computing Platforms

Dual in-memory computing of matrix-vector multiplication for accelerating neural networks

The Multilayer Neural Network Implementation Using SRAM-Based Reconfigurable Cognitive Computation Matrices

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IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm2 CIM-SRAM With Multi-Bit Analog Batch-Normalization

Cited by 8 publications

References 25 publications

Survey of Novel Architectures for Energy Efficient High-Performance Mobile Computing Platforms

Survey of Novel Architectures for Energy Efficient High-Performance Mobile Computing Platforms

Dual in-memory computing of matrix-vector multiplication for accelerating neural networks

The Multilayer Neural Network Implementation Using SRAM-Based Reconfigurable Cognitive Computation Matrices

Contact Info

Product

Resources

About

IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm² CIM-SRAM With Multi-Bit Analog Batch-Normalization