Image-rejection CMOS low-noise amplifier design optimization techniques

Nguyen, Trung‐Kien; Oh, Nam-Jin; Cha, Choong-Yul; Oh, Yong-Hun; Ihm, Gook-Ju; Lee, Sang‐Gug

doi:10.1109/tmtt.2004.840744

Cited by 56 publications

(15 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In other word, optimized matching for higher gain and minimum NF can be achieved simultaneously. Hence, we have the following equations: Im½Z opt ¼ ÀIm½Z in (11) Re½Z in ¼ Re½Z s (12) Im½Z in ¼ ÀIm½Z s (13) In these equations, Z s is the source impedance and can be expressed as follows:…”

Section: Design Methods and Noise Calculation For Lnamentioning

confidence: 99%

“…Then, L s is selected based on the value of C gs according to (11). With the selected value of C gs and L s , V gs can be determined using (12). Finally, L g is calculated using (13).…”

Section: Design Methods and Noise Calculation For Lnamentioning

confidence: 99%

“…To address these issues, research is being carried out to develop on-chip integrated filters. Attenuating the unwanted image frequency can be done by means of IR filter or IR architectures [8][9][10][11][12]. In this article, three LNA structures including cascode, folded cascade, and differential cascode are presented, and then IR filters are added to them.…”

Section: Three Lna Architectures With Ir Filtermentioning

confidence: 99%

See 2 more Smart Citations

Design and optimization of LNA topologies with image rejection filters

Golmakani

Mafinejad

Kouzani

2010

Int J RF and Microwave Comp Aid Eng

View full text Add to dashboard Cite

An important problem in designing RFIC in CMOS technology is the parasitic elements of passive and active devices that complicate design calculations. This article presents three LNA topologies including cascode, folded cascade, and differential cascode and then introduces image rejection filters for low-side and high-side injection. Then, a new method for design and optimization of the circuits based on a Pareto-based multiobjective genetic algorithm is proposed. A set of optimum device values and dimensions that best match design specifications are obtained. The optimization method is layout aware, parasitic aware, and simulation based. Circuit simulations are carried out based on TSMC 0.18 lm CMOS technology by using Hspice.

show abstract

Section: Design Methods and Noise Calculation For Lnamentioning

confidence: 99%

“…Then, L s is selected based on the value of C gs according to (11). With the selected value of C gs and L s , V gs can be determined using (12). Finally, L g is calculated using (13).…”

Section: Design Methods and Noise Calculation For Lnamentioning

confidence: 99%

Section: Three Lna Architectures With Ir Filtermentioning

confidence: 99%

See 1 more Smart Citation

Design and optimization of LNA topologies with image rejection filters

Golmakani

Mafinejad

Kouzani

2010

Int J RF and Microwave Comp Aid Eng

View full text Add to dashboard Cite

show abstract

“…Recently, some researchers have reported on LNA with notch filters [17][18][19][20][21][22]. Figure 6(a) shows an active second-order notch filter and a small signal equivalent circuit is shown in Figure 6(b).…”

Section: Notch Filtermentioning

confidence: 99%

“…Figure 6(a) shows an active second-order notch filter and a small signal equivalent circuit is shown in Figure 6(b). From Figure 6(b), the input impedance of the filter is given by [18] in,notch 1 where r g1 is the series gate resistance of M 1 , and R LF is the series resistance of on-chip inductor L f . Note that the negative term on the Equation (9) represents the negative resistance seen at the gate of transistor M 1 which is proportional to g m1 .…”

Section: Notch Filtermentioning

confidence: 99%

Design of Low Power CMOS LNA with Current-Reused and Notch Filter Topology for DS-UWB Application

Hsu¹,

Du²,

Chiu³

2012

WET

View full text Add to dashboard Cite

This paper presents the design of a low power LNA with second stage that uses a notch filter for DS-UWB application. The LNA employs a current reuse structure to reduce the power consumption and an active second order notch filter to produce band rejection in the 5 -6 GHz frequency band. The input reflection coefficient S11 and output reflection S22 are both less than -10 dB. The maximum power gain S21 is 15 dB while the maximum rejection ratio is over -10 dB at 4.8 GHz. The minimum noise figure is 5 dB. The input referred third-order intercept point (IIP3) is -7 dBm at 6 GHz. The power consumption is 6.4 mW from a 1-V power supply.

show abstract

A 3.4 dB NF k-band LNA with a tapped capacitor matching network in 65 nm CMOS technology

Yan

Zeng

et al. 2014

Int J RF and Microwave Comp Aid Eng

View full text Add to dashboard Cite

This article proposes a tapped capacitor network for low-noise amplifier (LNA) input matching which can provide much broader bandwidth than traditional ones. According to the design, the implemented LNA can realize noise match and power match simultaneously, which will broaden LNA's bandwidth without introducing larger noise than traditional ones. In addition, input pad parasitic capacitance can be absorbed by the network. Then a k-band LNA with the matching network designed in 65 nm CMOS technology is shown to demonstrate the performance of the matching network. The tested results show that frequency band of S 11 less than 210 dB is about 17 GHz and minimum NF is about 3.4 dB. V C 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 00:000-000, 2014.

show abstract

Image-rejection CMOS low-noise amplifier design optimization techniques

Cited by 56 publications

References 13 publications

Design and optimization of LNA topologies with image rejection filters

Design and optimization of LNA topologies with image rejection filters

Design of Low Power CMOS LNA with Current-Reused and Notch Filter Topology for DS-UWB Application

A 3.4 dB NF k-band LNA with a tapped capacitor matching network in 65 nm CMOS technology

Contact Info

Product

Resources

About