Image encryption design using FPGA

Leong, M.P.; Naziri, Siti Zarina Md; Perng, Shen-Yaw

doi:10.1109/iceese.2013.6895037

Cited by 12 publications

(4 citation statements)

References 7 publications

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“…31 An SPN-based chaotic system was used to encrypt the images on MATLAB platform by Belazi et al 32 An electronic code book (ECB) mode was utilized in Rijndael and RC6 block ciphers to encrypt images efficiently. 33 MATLAB was used to encrypt and decrypt the images on Altera DE2-70 board that was embedded together with the Altera's Cyclone II FPGA by Leong et al 34 Moreover, many algorithms such as RC5, RC6, MRC6, and Rijndael etc., have been used to encrypt digital and bitmap images. [35][36][37] The following studies in this table had lack of hardware implementation for such image encryption schemes.…”

Section: Related Workmentioning

confidence: 99%

“…An electronic code book (ECB) mode was utilized in Rijndael and RC6 block ciphers to encrypt images efficiently 33 . MATLAB was used to encrypt and decrypt the images on Altera DE2-70 board that was embedded together with the Altera’s Cyclone II FPGA by Leong et al 34 . Moreover, many algorithms such as RC5, RC6, MRC6, and Rijndael etc., have been used to encrypt digital and bitmap images 35 …”

Section: Introductionmentioning

confidence: 99%

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Low-area and high-speed hardware architectures of KLEIN lightweight block cipher for image encryption

2023

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.Internet of Things (IoT) connects a wide range of small devices over a large network, allowing for a wide range of applications. With the advancement of open-source public networks (such as IoT), image transmission for resource-constrained devices is becoming more insecure. In this paper, two hardware implementations for KLEIN block cipher are proposed that can provide security to encrypt different sets of images under resource-constrained applications (such as wireless sensor network, radio frequency identification, IoT etc.). An improvement in maximum operating frequency of 32.72% and 75.66% in the proposed serial and pipelined architectures is observed compared with the state-of-the-art design, respectively. The implemented pipelined architecture yields high throughput of 1840.15 MHz, and the serialized architecture implies 108 numbers of slices implemented on field-programmable gate array (FPGA) xc5vlx50t-3ff1136 device. On application-specific integrated circuit (ASIC) platform, the proposed serialized KLEIN implementation consumed less area in terms of gate equivalent. The existing solution was also subjected to changing correlation coefficients, number of pixels changing rate, unified average changing intensity, and entropy values. The simulation results validate the effectiveness of the performance of the proposed encryption scheme.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low-area and high-speed hardware architectures of KLEIN lightweight block cipher for image encryption

2023

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“…Finally, the quality of the encrypted image was demonstrated through the entropy, adjacent pixel correlation and histogram of the encrypted images. In [18], Leong M. P. et al proposed a chaotic image encryption scheme using the 1D logistic map. In this method, the encrypted image was obtained by applying the bitwise logical operators, AND, OR, XOR, an arithmetic multiplication and a combination of these logics.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation in an Altera's cyclone IV EP4CE6E22C8 FPGA board of a fast and robust cipher using combined 1D maps

Djomo,

Tiedeu,

Fotsing

2024

IET Image Processing

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This paper proposes an image encryption algorithm based on combined 1D chaotic maps. First, a permutation technique was applied. It was then reorganized into 1D matrices along the rows and columns respectively, which were then shuffled by computing the substituted position indices to obtain the scrambled image. Subsequently, a method of confusion of the scrambled image was used through another generated data map, combined with random sub‐matrices for diffusion, then resulting in an encrypted image. Finally, the proposed cryptosystem was implemented in a single kernel platform developed using the Nios II Software Build Tools processor for Eclipse. A hardware architecture was designed using the Qsys‐built tool which is available in the Quartus II 13.0sp1 environment. The developed single‐core system was implemented using the Cyclone IV EP4CE6E22C8. Robustness evaluation of the cryptosystem was performed through security analysis tests such as histogram analysis, correlation coefficient, differential analysis, and key space analysis to prove that it is of good quality, efficient, fast, and successfully resisting brute force attacks. The hardware performance analysis was also carried out. Then the cryptosystem is compared with those in the literature both in the hardware and security performance aspects.

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“…The internet, the most popular WAN, is the main channel for information transmission for various applications and services. Therefore, there is need for an effective security scheme to prevent vulnerability of information to unauthorized users that can compromise it at various levels of transmission as well as while in storage [2], [3]. To this end, one of the major functions of campus network management is based on network security.…”

Section: Introductionmentioning

confidence: 99%

Effective Multi-Layer Security for Campus Network

Alimi

2015

JCTECS

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Abstract-The development in different communication systems as well as multimedia applications and services leads to high rate of Internet usage. However, transmission of information over such networks can be compromised and security breaches such as virus, denial of service, unauthorized access, and theft of proprietary information which may have devastating impact on the system may occur if adequate security measures are not employed. Consequently, building viable, effective, and safe network is one of the main technical challenges of information transmission in campus networks. Furthermore, it has been observed that, network threats and attacks exist from the lower layers of network traffic to the application layer; therefore, this paper proposes an effective multi-layer firewall system for augmenting the functionalities of other network security technologies due to the fact that, irrespective of the type of access control being employed, attacks are still bound to occur. The effectiveness of the proposed network architecture is demonstrated using Cisco Packet Tracer. The simulation results show that, implementation of the proposed topology is viable and offers reasonable degree of security at different network layers.

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Image encryption design using FPGA

Cited by 12 publications

References 7 publications

Low-area and high-speed hardware architectures of KLEIN lightweight block cipher for image encryption

Low-area and high-speed hardware architectures of KLEIN lightweight block cipher for image encryption

Design and implementation in an Altera's cyclone IV EP4CE6E22C8 FPGA board of a fast and robust cipher using combined 1D maps

Effective Multi-Layer Security for Campus Network

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