Image compression algorithms using re-configurable logic

Heron, J.; Trainor, David; Woods, Roger

doi:10.1109/acssc.1997.680271

Cited by 6 publications

(3 citation statements)

References 5 publications

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“…Recently, a number of fixed-point FPGA-based DCT implementations have been proposed. The architecture proposed in [7] uses a recursive DCT implementation that lacks the parallelism required for high-speed throughput. The architectures presented in [8] offer significantly more parallelism by uniquely implementing each constant coefficient multiplier, but this architecture requires an unnecessarily large number of coefficient multipliers (thirty-two constant coefficient multipliers for an eight-point DCT).…”

Section: Dct Structures For Fpga-based Implementationsmentioning

confidence: 99%

“…Loeffler's DCT structure [9], see Figure 1, requires only twelve constant coefficient multipliers to implement an eight-point DCT (which is used in the JPEG and MPEG standards [1]). In contrast, the factorization employed in the FPGA implementations presented in [7,8] require thirty-two coefficient multiplications for an eight-point DCT.…”

Section: Dct Structures For Fpga-based Implementationsmentioning

confidence: 99%

“…The rapid prototyping method proposed in this paper can be used to design DCT implementations based on any of the structures presented in [7,8,9]. However these structures cannot be used in lossless compression applications and these structures require a large number of constant coefficient multipliers, which increases the hardware cost.…”

Section: A Low-cost Dct Structure That Permits Perfect Reconstructionmentioning

confidence: 99%

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Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform Approximations

Fox

Turner

2003

EURASIP J. Adv. Signal Process.

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A method for the rapid design of field programmable gate array (FPGA)-based discrete cosine transform (DCT) approximations is presented that can be used to control the coding gain, mean square error (MSE), quantization noise, hardware cost, and power consumption by optimizing the coefficient values and datapath wordlengths. Previous DCT design methods can only control the quality of the DCT approximation and estimates of the hardware cost by optimizing the coefficient values. It is shown that it is possible to rapidly prototype FPGA-based DCT approximations with near optimal coding gains that satisfy the MSE, hardware cost, quantization noise, and power consumption specifications

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Section: Dct Structures For Fpga-based Implementationsmentioning

confidence: 99%