IGZO TFT Gate Driver Circuit With Improved Output Pulse

Kim, Jin-Ho; Oh, Jongsu; Park, KeeChan; Jeon, Jae‐Hong; Kim, Yong−Sang

doi:10.1109/jeds.2018.2884920

Cited by 13 publications

(15 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Consequently, poly-Si and oxide TFTs have been researched for gate driver. [5][6][7][8][9][10] Low-temperature polycrystalline silicon (LTPS) TFTs have been mainly utilized for TFT backplane technology of small size display such as mobile display. LTPS TFTs exhibit high mobility and good stability.…”

Section: Introductionmentioning

confidence: 99%

Gate driver with low‐temperature polycrystalline silicon and oxide thin‐film‐transistor circuits for low power consumption and narrow bezel AMOLED displays

Kim

Jang

2022

J Soc Info Display

View full text Add to dashboard Cite

We propose a novel gate driver circuit using low-temperature polycrystalline silicon and oxide (LTPO) thin-film transistors (TFTs). The proposed circuit consists of only six TFTs, four p-type LTPS, and two n-type a-IGZO TFTs, without capacitor. The proposed circuit operates well when oxide TFTs have threshold voltage (V TH ) of À7.5 V, which is very depletion mode. Without bootstrapping, low gate bias stress occurs on TFTs in the proposed circuit. With dual gate (DG) structure of oxide TFTs, the stability of the proposed circuit is improved. In addition, by utilizing extremely low off-state current of oxide TFTs, ultra-low power consumption can be achieved. The total power consumption of the proposed gate driver is less than 100 mW under a-IGZO TFT's V TH of À6 V at 120 Hz 4k (3,840 Â 2,160) resolution display. The fabricated circuit works perfectly at a pulse width of 1 μs equivalent to operating speed of 500 kHz. The proposed circuit can be applied to ultra-high definition (UHD) and narrow bezel AMOLED display. K E Y W O R D Sdepletion mode, gate driver, low-temperature polycrystalline silicon and oxide (LTPO), power consumption, reliability, thin-film transistor (TFT)

show abstract

Section: Introductionmentioning

confidence: 99%

Gate driver with low‐temperature polycrystalline silicon and oxide thin‐film‐transistor circuits for low power consumption and narrow bezel AMOLED displays

Kim

Jang

2022

J Soc Info Display

View full text Add to dashboard Cite

show abstract

“…Above all, the Oxide-TFTs have a low off-current characteristic. So, it is possible to realize low power consumption of driving circuit (8).…”

Section: Introductionmentioning

confidence: 99%

61‐4: A New Pixel Circuit Based on LTPO Backplane Technology for Micro‐LED Display Using PWM Method

Jung

Hong

et al. 2021

Symp Digest of Tech Papers

Self Cite

View full text Add to dashboard Cite

show abstract

“…This method generates a driver IC of great complexity, increasing the cost of the display. Without modifying the existing driver IC, development of pull-down structures with low leakage current [14], [15] can completely turn off pull-down TFTs, avoiding an increase in the rising time of the scan pulse. The reduction in the leakage current of the pull-down structure, however, is inadequate for use in highresolution or high-frame-rate displays when the operating frequency of the gate driver increases.…”

Section: Introductionmentioning

confidence: 99%

Low-Leakage Capacitive Coupling Structure for a-Si:H Gate Driver With Less Delay of Clock Signals Used in AMLCDs

Deng

Liao

Chen

et al. 2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

This work proposes a hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) gate driver with a low-leakage capacitive coupling structure to reduce the delay of the clock signal. The proposed circuit suppresses the fluctuation in the gate node of the driving TFT induced by clock-feedthrough effect, reducing the leakage current that flows from the clock signal line to the power source line with a low voltage level. This reduction in the leakage current can improve the degradation in the voltage of the clock signal and thus avoid the increase in the rising time of the scan pulse. Measurements for extracting the drain current versus gate-to-source voltage (I D-V GS) curves of a fabricated a-Si:H TFT are made to establish a simulation TFT model by fitting the obtained curves. For the same parameters of the TFTs and capacitances, the leakage current and the rising time of the output waveform of the proposed circuit are 45.45% and 21.36% lower, respectively, than those of previously developed gate driver. INDEX TERMS a-Si:H TFTs, capacitive-coupling effect, clock-feed-through effect, gate driver, leakage current.

show abstract

IGZO TFT Gate Driver Circuit With Improved Output Pulse

Cited by 13 publications

References 14 publications

Gate driver with low‐temperature polycrystalline silicon and oxide thin‐film‐transistor circuits for low power consumption and narrow bezel AMOLED displays

Gate driver with low‐temperature polycrystalline silicon and oxide thin‐film‐transistor circuits for low power consumption and narrow bezel AMOLED displays

61‐4: A New Pixel Circuit Based on LTPO Backplane Technology for Micro‐LED Display Using PWM Method

Low-Leakage Capacitive Coupling Structure for a-Si:H Gate Driver With Less Delay of Clock Signals Used in AMLCDs

Contact Info

Product

Resources

About