IEEE Standard 1149.1 Test Access Port And Boundary Scan Implementation In High Density CMOS Gate Arrays

Abstract

This paper summarizes the implementation of IEEE 1149.1 test logic in Motorola ASIC Division's H4C SeriesTM of threelayer metal sub-micron (0.7 p effective channel length) CMOS gate arrays and advantages. The Boundary Scan Chain (BSC) logic and buffers for the BSC signals are implemented in the Periphery of gate arrays. This led to compact implementation of the BSC cells and interconnections, higher utilization of the core area for system logic, and reduction in delay in the system signal path through the BSC logic. 0-7803-0246-X/92 $3.00 1992 IEEE