Identifying the minor set cover of dense connected bipartite graphs via random matching edge sets

Abstract

Using quantum annealing to solve an optimization problem requires minor embeddings of a logic graph into a known hardware graph. In an effort to reduce the complexity of the minor embedding problem, we introduce the minor set cover (MSC) of a known graph G: a subset of graph minors which contain any remaining minor of the graph as a subgraph. Any graph that can be embedded into G will be embeddable into a member of the MSC. Focusing on embedding into the hardware graph of commercially available quantum annealers, we establish the MSC for a particular known virtual hardware, which is a complete bipartite graph. We show that the complete bipartite graph KN,N has a MSC of N minors, from which KN+1 is identified as the largest clique minor of KN,N . The case of determining the largest clique minor of hardware with faults is briefly discussed but remains an open question.

Application of Quantum Annealing to Nurse Scheduling Problem

“…Additional steps address the transformation of the logical input into a physical representation which can be embedded into the hardware [19]. This step, known as minor embedding, depends strongly on the connectivity of the vertex set V and the sparsity of the chimera layout [20,21]. Consequently, additional auxillary spin variables may be introduced during embedding to ensure logical connections are satisfied [22].…”

Recall Performance for Content-Addressable Memory Using Adiabatic Quantum Optimization

“…The mapping from a set of logical qubits to set of physical qubits represents the problem of minor graph embedding, which seeks a representation of the connectivity for the logical Ising Hamiltonian within the physical hardware. Many different methods have been developed for solving the minor graph embedding within the context of the Chimera target graph [39][40][41][42][43]. We use a deterministic method for mapping a complete graph into the Chimera layout that is known to provide the least overhead with respect to number of physical qubits and, therefore, enables us to test the largest problem sizes available within this device [40].…”

“…This changes the original problem with the intent of being easier to map to the hardware graph while keeping the stored memories as energetic minima. The bipartite structure is especially appealing due to ease of embedding into the hardware graph [42,43]. Reducing the encoded interactions between qubits also reduces interference between stored memories.…”

Instruction Set Architectures for Quantum Processing Units

“…The latest D-Wave 2000Q hardware system is composed of approximately 2000 physical qubits arranged in a topology called Chimera (see Fig. 2) [6,7]. This is a sufficient number of qubits to enable direct comparison with modest-sized domain-specific problems.…”

“…While hardware connectivity constraints don't allow any arbitrary physical qubit to interact with another arbitrary physical qubit, any qubit active in the D-Wave architecture can fill the role of the first or second qubit, thus we must assume that the remaining bits of the message are equally divided between the first and second qubit. Assuming a 64-bit architecture, each qubit would be allocated 27 bits of width, allowing for 2 27 or 1.34217728 * 10 8 qubits in the system which would allow a fully connected system of approximately 4096 logical qubits if the physical qubits had the same degree of inter-unit-cell connectivity and double the intra-unit-cell connectivity as available in the D-Wave 2000Q [7].…”