Identifying Highly Popular Content Improves Forwarding Speed of NDN Software Router

Takemasa, Junji; Taniguchi, Kenichi; Hasegawa, Takeshi

doi:10.1109/glocomw.2016.7848926

Cited by 5 publications

(9 citation statements)

References 11 publications

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“…Cache admission decides whether an arriving packet should be inserted to a cache or not, whereas cache eviction determines the victim packet to be evicted from a cache. Cache admission algorithms, for instance, are proposed in [10], [16].…”

Section: B Packet-level Caching With Cache Admissionmentioning

confidence: 99%

“…We use Filter [10] as a cache admission algorithm because it is sufficiently lightweight in terms of time complexity. Specifically, Filter counts the number of recent packet arrivals as the frequency of the packets and admits a packet if its frequency exceeds a predefined threshold θ.…”

Section: B Packet-level Caching With Cache Admissionmentioning

confidence: 99%

“…Second, a two level of caching is time-consuming and thus such caching algorithm may be a bottleneck of high-speed router implementations. For example, Takemasa et al experimentally show that simple FIFO eviction consumes about 800 cycles at Intel CPUs [10]. Thus complicated cache algorithms like OPC is not suitable for high-speed forwarding.…”

Section: Introductionmentioning

confidence: 99%

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A Packet-Level Caching Algorithm for Mitigating Negative Effects Caused by Large Objects in ICN Networks

2020

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Increase in the size of content due to the emergence of bandwidth-intensive applications leads to a problematic phenomenon of packet-level caching which is called looped replacement. This causes a waste of cache usage and results in caching performance degradation. The goals of the paper are twofold: identifying the root cause of looped replacement and mitigating it. In order to achieve the goals, we analytically investigate not only how looped replacement occurs, but also how cache hit probability decreases. According to the analysis, we propose to use cache admission, which only admits packets arriving frequently to a cache, as a countermeasure against both problems. Finally, we develop an analytical model of packetlevel caching with cache admission, and theoretically proves that cache admission mitigates these problems and improves cache hit probability.

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Section: B Packet-level Caching With Cache Admissionmentioning

confidence: 99%

Section: B Packet-level Caching With Cache Admissionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Packet-Level Caching Algorithm for Mitigating Negative Effects Caused by Large Objects in ICN Networks

2020

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“…As the second step, we address how to achieve high speed for LFU-based cache algorithms, of which computation is well known to be heavy. In order to address this issue, we first analyze how individual blocks of a simple FIFO cache eviction algorithm, which is much lighter than LFU-based cache algorithms, spends computation time based on our previous study [11], where we analyzed computation time of individual function blocks of the current state-of-the-art NDN router implementation [3]. This objective is to know how even a simple FIFO cache eviction algorithm spends computation time on a PC based platform.…”

Section: Introductionmentioning

confidence: 99%

“…In our previous study [11], we have developed a lightweight cache admission algorithm, Filter, which consumes about only 100 CPU cycles, and have compared Filter with another cache algorithms, the TinyLFU admission algorithm [13] and the FIFO eviction algorithm, in terms of a part of computation time which is specific to cache admission or eviction. In this paper, we extend the study [11] from the following three aspects: First, we quantitatively evaluate computation time of cache admission and cache eviction algorithms by analyzing packet processing flows of an NDN router with both cache eviction and admission algorithms to understand their influences on total computation time of packet processing. Second, we prove the efficiency of Filter by comparing it with a well-known cache admission algorithm in terms of both computation time and cache hit rate to show that Filter is one of the lightest cache admission algorithms.…”

Section: Introductionmentioning

confidence: 99%

Lightweight Cache Admission Algorithm for Fast NDN Software Routers

Takemasa

Hasegawa

2019

Journal of Information Processing

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This paper addresses how to design a cache algorithm for achieving high cache hit rate and high packet forwarding rate of Named Data Networking (NDN) software routers. Although sophisticated cache eviction algorithms like LFU and Adaptive Replacement Cache (ARC) successfully achieve high cache hit rate, they incur heavy computational overheads to choose a victim Data packet from the cache. In contrast, cache admission is expected to achieve high cache hit rate with lightweight computation since it decides simply whether an incoming Data packet should be inserted into the cache or not. In this paper, we design a frequency-based cache admission algorithm, Filter, with lightweight computation by simply counting frequencies of incoming Data packets in a fixed time window. A simulation-based evaluation proves that Filter achieves high cache hit rate comparable to sophisticated cache eviction algorithms like ARC. By implementing a prototype of an NDN software router with Filter, we validate that the NDN router with Filter improves packet forwarding rate compared to that with a sophisticated cache eviction algorithm like ARC and even that with a simple one like FIFO.

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Load Balancing for Stateful Forwarding by Mitigating Heavy Hitters: A Case for Multi-Threaded NDN Software Routers

2020

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Equal load balancing for dispatching incoming packets to multiple threads is a crucial requirement in the stateful forwarding of multi-threaded software routers to achieve high-speed forwarding and low packet loss simultaneously. However, equal load balancing is not trivial for Named Data Networking (NDN) routers because of their stateful forwarding. In other words, the consistency of flow states should be maintained so that multiple threads do not access the states simultaneously. Sharding, wherein packets of the same flow are dispatched to the same thread while keeping loads of threads equal, has been proposed; however, in this study, we reveal that heavy hitters like popular content packets cause load imbalance, which may eventually cause packet losses. This study proposes a load balancing mechanism for NDN routers by exploiting the fact that states of flows need not be rigorously maintained when content packets are returned from caches at intermediate routers.

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Identifying Highly Popular Content Improves Forwarding Speed of NDN Software Router

Cited by 5 publications

References 11 publications

A Packet-Level Caching Algorithm for Mitigating Negative Effects Caused by Large Objects in ICN Networks

A Packet-Level Caching Algorithm for Mitigating Negative Effects Caused by Large Objects in ICN Networks

Lightweight Cache Admission Algorithm for Fast NDN Software Routers

Load Balancing for Stateful Forwarding by Mitigating Heavy Hitters: A Case for Multi-Threaded NDN Software Routers

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