Identification of Threshold Functions and Synthesis of Threshold Networks

Gowda, Tejaswi; Vrudhula, Sarma; Kulkarni, Niranjan; Berezowski, Krzysztof S.

doi:10.1109/tcad.2010.2100232

Cited by 38 publications

(25 citation statements)

References 21 publications

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“…By performing reductions in this area, the algorithm proposed typically achieved over 20% fewer clusters, and 40% fewer buffers. Future research will explore using more robust methods for identifying threshold functions such as Gowda et al [2011]; Palaniswamy and Tragoudas [2012], and Palaniswamy et al [2010], in conjunction with balancing paths using the algorithm proposed in this article.…”

Section: Resultsmentioning

confidence: 99%

“…Namely, through the replication of gates, clusters can be formed even on branching nodes, which previous proposals could not cluster. While recent algorithms such as Gowda et al [2011], Palaniswamy et al [2010], and Gowda and Vrudhula [2008] abstract the gates to functions, this algorithm works at the gate level. Working from a structured netlist allows for better predictions of the synchronization cost for clustering a set of nodes.…”

Section: Introductionmentioning

confidence: 99%

“…Without this knowledge, synchronization costs cannot be properly predicted. Thus, the proposed technique does not apply the base function techniques that are found in Gowda et al [2011], Palaniswamy et al [2010], and Gowda and Vrudhula [2008].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Nanopipelined threshold network synthesis

Pierce

Tragoudas

2014

J. Emerg. Technol. Comput. Syst.

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Threshold logic gates allow for complex multiinput functions to be implemented using a single gate thereby reducing the power and area of a circuit. Clocked threshold gates are nanopipelined to increase network throughput. It is shown that synthesis methods that do not consider the synchronization of the nanopipeline can produce an enormous amount of buffers. The proposed algorithm synthesizes a Boolean network into a nanopipelined threshold logic network by minimizing not only the number of combinational clusters but also the associated buffer insertion overhead.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Nanopipelined threshold network synthesis

Pierce

Tragoudas

2014

J. Emerg. Technol. Comput. Syst.

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“…Many synthesis techniques have been proposed for implementing circuits with TLGs [Oliveira and Sangiovanni-Vincentelli 1991;Zhang et al 2005;Franco et al 2006;Subirats et al 2008;Avedillo and Quintana 2004;Gowda and Vrudhula 2008;Gowda et al 2011]. Besides Oliveira and Sangiovanni-Vincentelli [1991], all these techniques form multilevel TNs.…”

Section: Introductionmentioning

confidence: 99%

Improved Threshold Logic Synthesis Using Implicant-Implicit Algorithms

Palaniswamy

Tragoudas

2014

J. Emerg. Technol. Comput. Syst.

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Existing threshold logic synthesis methods decompose larger input functions into smaller input functions and perform synthesis for them. It is shown that significantly larger input functions can be synthesized by implementing the existing methods in an implicant-implicit manner. Experimental results on the ISCAS 85 benchmarks show that this impacts the synthesis cost, which drops significantly. More specifically, as the size of the functions that can be handled by the synthesis algorithm increases, the number of threshold logic gates required to implement very large input functions decreases. In addition, the total weight decreases and the performance is improved.

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“…has been advanced as well. Different synthesis methodologies have been proposed to synthesize multi-level threshold logic networks [2,18,20,21,29,46]. In the field of verification and testing, efforts have been made as well [19,22,47].…”

Section: Introductionmentioning

confidence: 99%

Sensitization criterion for threshold logic circuits and its application

Tsai¹,

Wang²,

Huang³

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Threshold logic has been known as an alternative representation of Boolean logic due to its compactness characteristic. Recently, the developments in advanced nanotechnologies have also promised efficient implementations of threshold logic gates. Thus, many synthesis methodologies for threshold logic circuits have been proposed. Since threshold logic has a different mechanism in functional evaluation compared to the traditional Boolean logic, a threshold logic gate can represent a more complex function. As a result, the sensitization criterion in threshold logic circuits is also different. In this work, we propose a sensitization criterion for threshold logic circuits, and show its application to the static timing analysis problem. The experimental results show the accuracy of the proposed criterion.

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Identification of Threshold Functions and Synthesis of Threshold Networks

Cited by 38 publications

References 21 publications

Nanopipelined threshold network synthesis

Nanopipelined threshold network synthesis

Improved Threshold Logic Synthesis Using Implicant-Implicit Algorithms

Sensitization criterion for threshold logic circuits and its application

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