Identification and exploitation of symmetries in DSP algorithms

Eijk, C.A.J. van; Jacobs, E.T.A.F.; Mesman, B.; Timmer, A.H.

doi:10.1109/date.1999.761190

Cited by 3 publications

(1 citation statement)

References 14 publications

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“…For the proof that Transformation 1 preserves feasibility, as well as for a more detailed discussion and additional techniques, we refer the interested reader to [Van Eijk et al 1998]. …”

Section: Definition 3 (Automorphism) An Automorphism Is a Bijective mentioning

confidence: 99%

Constraint analysis for code generation

Eijk

Mesman

Pinto

et al. 2000

ACM Trans. Des. Autom. Electron. Syst.

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Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by signal processing applications and resource constraints implied by the processor architecture. In particular, limited resource availability (e.g., registers) poses a problem for traditional methods that perform code generation in separate stages (e.g., scheduling followed by register binding). This separation often results in suboptimality (or even infeasibility) of the generated solutions because it ignores the problem of phase coupling (e.g., since value lifetimes are a result of scheduling, scheduling affects the solution space for register binding). As a result, traditional methods need an increasing amount of help from the programmer (or designer) to arrive at a feasible solution. Because this requires an excessive amount of design time and extensive knowledge of the processor architecture, there is a need for automated techniques that can cope with the different kinds of constraints during scheduling. By exploiting these constraints to prune the schedule search space, the scheduler is often prevented from making a decision that inevitably violates one or more constraints. FACTS is a research tool developed for this purpose. In this paper we will elucidate the philosophy and concepts of FACTS and demonstrate them on a number of examples.

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“…For the proof that Transformation 1 preserves feasibility, as well as for a more detailed discussion and additional techniques, we refer the interested reader to [Van Eijk et al 1998]. …”

Section: Definition 3 (Automorphism) An Automorphism Is a Bijective mentioning

confidence: 99%

Constraint analysis for code generation

Eijk

Mesman

Pinto

et al. 2000

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

show abstract

Designing electronic engines with electronic engines: 40 years of bootstrapping of a technology upon itself

Jess

2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Solving difficult instances of boolean satisfiability in the presence of symmetry

Aloul

Ramani

Markov

et al. 2003

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Research in algorithms for Boolean satisfiability (SAT) and their implementations [45,41,10] has recently outpaced benchmarking efforts. Most of the classic DIMACS benchmarks [21] can now be solved in seconds on commodity PCs. More recent benchmarks [54] take longer to solve due of their large size, but are still solved in minutes. Yet, small and difficult SAT instances must exist if P NP. To this end, our work articulates SAT instances that are unusually difficult for their size, including satisfiable instances derived from Very Large Scale Integration (VLSI) routing problems. With an efficient implementation to solve the graph automorphism problem [39,50,51], we show that in structured SAT instances difficulty may be associated with large numbers of symmetries.We point out that a previously published symmetry-detection mechanism [18] based on a reduction to the graph automorphism problem often produces many spurious symmetries. Our work contributes two new reductions to graph automorphism, which detect all correct symmetries detected previously [18] as well as phase-shift symmetries not detected earlier. The correctness of our reductions is rigorously proven, and they are evaluated empirically.We also formulate an improved construction of symmetry-breaking clauses in terms of permutation cycles and propose to use only generators of symmetries in this process. These ideas are implemented in a fully automated flow that first detects symmetries in a given SAT instance, pre-processes it by adding symmetry-breaking clauses and then calls a state-of-the-art backtrack SAT solver. Significant speed-ups are shown on many benchmarks versus direct application of the solver.In an attempt to further improve the practicality of our approach, we propose a scheme for fast "opportunistic" symmetry detection and also show that considerations of symmetry may lead to more efficient reductions to SAT in the VLSI routing domain.

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Identification and exploitation of symmetries in DSP algorithms

Abstract: Abstract

Cited by 3 publications

References 14 publications

Constraint analysis for code generation

Constraint analysis for code generation

Designing electronic engines with electronic engines: 40 years of bootstrapping of a technology upon itself

Solving difficult instances of boolean satisfiability in the presence of symmetry

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