IDAMC: A Many-Core Platform with Run-Time Monitoring for Mixed-Criticality

Motruk, Boris; Diemer, Jonas; Buchty, Rainer; Ernst, Rolf; Berekovic, Mladen

doi:10.1109/hase.2012.19

Cited by 25 publications

(20 citation statements)

References 15 publications

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“…IDAMC [17] is a source-routed NoC using credit-based flow control and virtual channel input buffers together to provide GS. IDAMC provides GS connections by implementing the Back Suction scheme [18], which prioritizes noncritical traffic while the critical traffic progresses to meet the deadline.…”

Section: Related Workmentioning

confidence: 99%

“…In the rare case that a schedule needs to be transmitted to the slave NIs, our approach is still comparable. The maximum schedule transmission time in Table 7 shows the comparison of the Argo 2.0 implementation to the TDMbased NoCs aelite and dAElite [9], and to the IDAMC [17] NoC that uses a classic router designed with virtual channel buffers and flow control. The table shows the results of the four designs for one router and one NI and the number of supported TDM slots and connections per node.…”

Section: Worst-case Reconfiguration Timementioning

confidence: 99%

See 1 more Smart Citation

A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

Sørensen

Pezzarossa

Schoeberl

et al. 2017

Journal of Systems Architecture

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Section: Related Workmentioning

confidence: 99%

Section: Worst-case Reconfiguration Timementioning

confidence: 99%

A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

Sørensen

Pezzarossa

Schoeberl

et al. 2017

Journal of Systems Architecture

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show abstract

“…This can be further exploited to implement a heterogeneous multi-core system [1]. These system may consist of multiple soft CPUs with a custom interconnect [2,3]. Compared to a single feature rich CPU, multiple lightweight CPUs have the potential to improve performance of multithreaded applications implemented on FPGAs.…”

Section: Introductionmentioning

confidence: 98%

Generation of multi-core systems from multithreaded software

Wold

Tørresen

Agne

2013

2013 23rd International Conference on Field Programmable Logic and Applications

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A heterogeneous system with soft CPU tailored to the individual threads of the application, while still software based, offers the potential for improved performance and resource utilization over a homogeneous system. In this paper we present a method to automatically create a heterogeneous multi-core system from a multithreaded software application. The resulting system consists of processing elements based on customized MIPS soft CPUs coupled with their respective programs. Using instruction set architecture (ISA) subsetting, we adapt the individual soft CPUs to the specific computations they have to perform. We have carried out a case study with a constraint solver application for which we find a performance increase of 1.54 accompanied with an area reduction of 22.5% compared to a homogeneous multicore system. We also present an automated toolchain that generates synthesizable IP-cores from software threads with little additional development overhead.

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“…In NoCs, memory operations and I/O are packets traversing a network. On-Chip networks exist in a variety of topologies ranging from meshes, as seen in many-core architectures [1], to topologies optimized for a given MPSoC architecture [2]. Being a central component, the correct operation of the NoC is essential for the MPSoC.…”

Section: Introductionmentioning

confidence: 99%

“…NoC-based MPSoC platforms are currently being evaluated for mixed-critical real-time embedded systems [1], [4], [5]. Regulated by safety standards [6]- [8], such systems must meet strict real-time, resilience and integrity requirements.…”

Section: Introductionmentioning

confidence: 99%

Providing Integrity in Real-Time Networks-on-Chip

Rambo

Shang

Ernst

2019

IEEE Trans. VLSI Syst.

Self Cite

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Mixed-critical real-time systems must meet strict integrity, resilience and timing constraints, as specified by safety standards. Due to the increasing threat of random hardware faults, efficiently achieving high reliability and dependability calls for cross-layer fault-tolerance solutions. This work introduces the Advanced Integrity Q-service (AIQ), a mechanism to ensure the integrity and predictability of on-Chip communication under random hardware faults. Devised for cross-layer and hierarchical fault-tolerance solutions, AIQ realizes low-overhead error detection in hardware and delegates error handling to arbitrary strategies in software. Experimental evaluation featuring benchmark applications and an industrial avionics use case shows that AIQ operates with high reliability and availability and low hardware and performance overheads. In a many-core mixed-critical platform under expected real-time scenarios, AIQ performs with execution time overhead between 1.4% and 7.1%.

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IDAMC: A Many-Core Platform with Run-Time Monitoring for Mixed-Criticality

Cited by 25 publications

References 15 publications

A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

Generation of multi-core systems from multithreaded software

Providing Integrity in Real-Time Networks-on-Chip

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