IC performance prediction from electrical test measurements

Abstract

A model for integrated circuit (IC) binning has been built using measurements collected on a high volume manufacturing line. This model uses electrical measurements collected before packaging in order to predict the high speed performance of manufactured parts before final test. The applications of the model include aiding the packaging decision, production planning and scheduling, process characterization and control and design for manufacturability. IntroductionAs integrated circuit dimensions shrink, circuit performance variation due to random fluctuations in the fabrication process becomes increasingly important [ 1,2,3]. This paper discusses a method for modeling the performance of fabricated integrated circuits in terms of measurable process parameters. These models are meant to cover the entire range of process variation. A commercial 1 Mbit CMOS EPROM is used as the test vehicle for this experiment.The intended application for the model is for binning manufactured parts. Commodity ICs, such as memories, microprocessors, EPLDs, etc., are performance tested and then priced accordingly. In-line measurements and electrical test results for a manufactured wafer can be used to predict circuit performance before final wafer test. This will allow binning early in the fabrication process.The ability to perform in-line binning is important in manufacturing planning, since it will make possible the expediting of higher performance wafers through the fabrication line.A second application of this model is for IC Design for Manufacturability [4,51. This can be accomplished by using this modeling technique to characterize the sensitivity of a new IC design to the variation of each critical process parameter.Previous related work has focused on reducing the amount of testing required by eliminating redundant measurements [6,7]. However, the issue of predicting performance early in the manufacturing cycle is not addressed. The work presented here uses measurements available before final test. The particular example discussed in this paper uses wafer level electrical test data, with the future goal of using in-line data for performance testing.The underlying thesis of this work is that measurable variation in process parameters causes the performance variation in fabricated ICs. Therefore, the contribution of this work is that the performance model is developed from measurements on a high-volume manufacturing line, and not process and device simulation results, as is typical in previous publications [ 1,2,3,6,7]. This ensures that the pertinent parameters are measurable with a small error, and that they explain the variation seen on an actual fab line.This paper is organized as follows. First, a general overview of the method will be given. Next, descriptions of fabrication line variation, then the experimental design used to develop the model will be discussed. The results will then be presented, followed by our conclusions and plans for future work.