“…IBM z15 [9,72,101] and prior system generations [10,11,17,28,50,51,80,95,96] implemented shared physical L3 caches on the processor chip, and had a separate chip that implemented a large L4 cache. The Telum design implements all of that logic in a single chip, and opts to quadruple the L2 cache to 32 MB with very low latency.…”