IBM POWER9 system software

Jann, Joefon; Mackerras, Paul; Ludden, John M.; Gschwind, Michael; Ouren, Wade; Jacobs, Stuart; Veale, Brian F.; Edelsohn, David

doi:10.1147/jrd.2018.2846959

Cited by 6 publications

(4 citation statements)

References 4 publications

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“…Hashed page tables (HPTs) are an alternative design to radix page tables. They have been implemented in the IBM PowerPC, HP PA-RISC, and Intel Itanium (IA-64) [26,40,43,49,50]. In HPTs, address translation is performed by hashing the virtual page number, indexing a hash table, and reading the physical page number from the entry.…”

Section: Hashed Page Tablesmentioning

confidence: 99%

“…In theory, they perform address translation in one step, by hashing a virtual page number into a hash key, accessing the corresponding table entry, and reading the physical page number from there. HPTs have been implemented in the past [26,27,35,40,41,43,50] and recent work [79,89] has solved some of their traditional shortcomings [14,35,89].…”

Section: Introductionmentioning

confidence: 99%

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Parallel virtualized memory translation with nested elastic cuckoo page tables

Stojkovic

Skarlatos

Kokolis

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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A major reason why nested or virtualized address translations are slow is because current systems organize page tables in a multi-level tree that is accessed in a sequential manner. A nested translation may potentially require up to twenty-four sequential memory accesses. To address this problem, this paper presents the first page table design that supports parallel nested address translation. The design is based on using hashed page tables (HPTs) for both guest and host. However, directly extending a native HPT design to a nested environment leads to minor gains. Instead, our design solves a new set of challenges that appear in nested environments. Our scheme eliminates all but three of the potentially twenty-four sequential steps of a nested translation-while judiciously limiting the number of parallel memory accesses issued to avoid over-consuming cache bandwidth. As a result, compared to conventional nested radix tables, our design speeds-up the execution of a set of applications by an average of 1.19x (for 4KB pages) and 1.24x (when huge pages are used). In addition, we also show a migration path from current nested radix page tables to our design. CCS CONCEPTS• Software and its engineering → Operating systems; Virtual memory; • Computer systems organization → Architectures.

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Section: Hashed Page Tablesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Parallel virtualized memory translation with nested elastic cuckoo page tables

Stojkovic

Skarlatos

Kokolis

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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“…Hashed page tables [22,33,39,40,68] have been implemented in the IBM PowerPC, HP PA-RISC, and Intel Itanium architectures. The support for a hashed page table in the Itanium architecture was referred to as the long-format Virtual Hash Page Table (VHPT) [23,28,35].…”

Section: Hashed Page Tablesmentioning

confidence: 99%

“…A natural approach would be to replace the radix page table with a hashed page table, which stores virtual-to-physical translations in a hash table [22,33,39,40,68]. Unfortunately, hashed page tables have been plagued by a number of problems.…”

Section: Introductionmentioning

confidence: 99%

Elastic Cuckoo Page Tables

Skarlatos

Kokolis

et al. 2020

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Syste

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The unprecedented growth in the memory needs of emerging memory-intensive workloads has made virtual memory translation a major performance bottleneck. To address this problem, this paper introduces Elastic Cuckoo Page Tables, a novel page table design that transforms the sequential pointer-chasing operation used by conventional multi-level radix page tables into fully-parallel look-ups. The resulting design harvests, for the first time, the benefits of memorylevel parallelism for address translation. Elastic cuckoo page tables use Elastic Cuckoo Hashing, a novel extension of cuckoo hashing that supports efficient page table resizing. Elastic cuckoo page tables efficiently resolve hash collisions, provide process-private page tables, support multiple page sizes and page sharing among processes, and dynamically adapt page table sizes to meet application requirements.We evaluate elastic cuckoo page tables with full-system simulations of an 8-core processor using a set of graph analytics, bioinformatics, HPC, and system workloads. Elastic cuckoo page tables reduce the address translation overhead by an average of 41% over conventional radix page tables. The result is a 3-18% speed-up in application execution. CCS Concepts. • Software and its engineering → Operating systems; Virtual memory; • Computer systems organization → Architectures.

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