IBM POWER9 processor and system features for computing in the cognitive era

Heterogeneity aware power abstractions for dynamic power dominated FinFET‐based microprocessors

“…Designs of varying degrees of complexity are used as representatives of next‐generation high‐performance microprocessor designs [7, 8]. They vary in terms of the size of the design as well as the amount of clock gating present in the designs.…”

“…We put additional focus in the context of aggressive clock‐gating techniques and further use‐cases like dynamic power signature driven localised self‐heating analysis and high‐level power models used for the co‐design of systems. In FinFET‐based high‐performance microprocessors, dynamic power is the significant contributor to overall chip power consumption [6–8]. In Fig.…”

Signal integrity analysis and Peripheral Component Interconnect Express backplane link compliance assessment

“…The link being researched in this work is part of a PCI‐express gen4 interface for the data storage system being designed by YADRO. The link is comprised of three PCBs: a POWER9 base board, 21,22 a passive backplane and an add‐in card (AIC) with a PCI‐express gen4 Broadcom switch. The base board and the add‐in card are connected to the backplane PCB using a high‐speed edge and corner vertical SMT connectors, respectively.…”