$I_{D}$– $V_{\rm GS}$-Based Tools to Profile Charge Distributions on NROM Memory Devices

Abstract

NROM memory cells are proposed as promising nonvolatile memories. Even though these devices should have a better endurance than their floating-gate counterparts, issues have risen due to the presence of both electrons and holes, for the control of their relative position and spread in the charge-trapping material. Thus, a deep knowledge of charge distribution features is crucial for program/erase bias optimization, reliability predictions, and future scaling. In this paper, we will introduce and discuss two tools based on I D -V GS curves (i.e., subthreshold slope and I D temperature effects) which will be used to profile charge distribution. Simple formulas allowing to calculate charge distribution length and density will be derived, and their accuracy will be tested for cells programmed at different levels and under different bias conditions. Finally, we will discuss the limits of both tools when applied to erased NROM cells, i.e., cells having both electron and hole distributions in the nitride region above the junction.Index Terms-Device simulations, Flash memory, gate-induced drain leakage (GIDL), nitride-based trapping storage, NROM, semiconductor device reliability, trapped charge profiling.

Thermal stability of paramagnetic defect centers in amorphous silicon nitride films

“…A morphous silicon nitride films have attracted considerable attention as a promising solution for charge trapping layers in high-density nonvolatile semiconductor memories. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] In nitride-based charge trapping memories, electron and hole trapping processes induced by defect centers distributed in silicon nitride films are applied to data storage. This application requires an understanding of the nature of the defect centers.…”

Study Trapped Charge Distribution in P-Channel Silicon–Oxide–Nitride–Oxide–Silicon Memory Device Using Dynamic Programming Scheme

“…Conventionally, many studies have been done for the charge distribution in SiN layer during programming in n-channel silicon-oxide-nitride-oxide-silicon (SONOS) devices, [1][2][3][4] using several methods, [5][6][7][8][9][10][11][12] such as comparison between sub-threshold and gate induced drain leakage (GIDL) characteristics, 1,6,7) studying V t difference between forward and reverse read. 4,11,12) These studies have revealed that injected charges were locally concentrated near to drain side until SiN trapped states are fully occupied by trapped charge.…”

Ultraviolet Light-Induced Conduction Current in Silicon Nitride Films

“…Amorphous silicon nitride (Si 3 N 4 ) films have received considerable attention as charge tapping dielectric layers in silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory (NVM) devices. [1][2][3][4][5][6][7][8] In order to achieve excellent memory characteristics and reliability in SONOS type devices, it is important to understand the charge transport mechanisms involved and the role of point defects in silicon nitride films. Several authors have reported that charge transport in thick silicon nitride films at high fields and high temperatures can be attributed to Poole-Frenkel (PF) emission.…”