Hypervisor based Memory Introspection: Challenges, Problems and Limitations

Luţaş, Andrei; Ticle, Daniel; Cret, Octavian

doi:10.5220/0006125802850294

Cited by 3 publications

(1 citation statement)

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“…To address the downsides of shadow page tables, the Second Level Address Translation (SLAT) utilizes two levels of translations [103], see Figure 9: i) guest logical address to guest physical address; and ii) guest physical (or host virtual) address to host physical address. SLAT is typically implemented in hardware, e.g., Intel® Extended Page Tables (EPT) [104] and AMD Nested Pages [105], that is used by the hypervisors for efficient address translation between guest VM and host (machine) physical address.…”

Section: B: Second-level Address Translation (Slat)mentioning

confidence: 99%

Operating Systems and Hypervisors for Network Functions: A Survey of Enabling Technologies and Research Studies

et al. 2022

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Scalable and flexible communication networks increasingly conduct the packet processing for Network Functions (NFs) in General Purpose Computing (GPC) platforms. The input/output (I/O)-intensive and latency-sensitive packet processing is challenging for the operating systems and hypervisors running on GPC platforms. This article surveys the existing enabling technologies and research studies on operating system and hypervisor aspects that directly influence the packet processing for NFs on GPC platforms. We organize this survey according to the main categories abstraction approach, memory access, and I/O strategy. We further categorize abstraction approach technologies and research studies into the categories operation systems, hypervisors, and containers. We partition the memory access category into the two subcategories of memory allocation and memory access, while we partition the I/O strategy category into the sub-categories I/O device virtualization and I/O device access. Our survey gives a comprehensive summary of the capabilities and limitations of the existing enabling technologies and researched approaches for abstraction, memory access, and I/O for NF packet processing. We outline critical future research directions for advancing NF packet processing on GPC platforms.

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Section: B: Second-level Address Translation (Slat)mentioning

confidence: 99%