Hyperchaotic Chameleon: Fractional Order FPGA Implementation

Rajagopal, Karthikeyan; Karthikeyan, Anitha; Duraisamy, Prakash

doi:10.1155/2017/8979408

Cited by 53 publications

(41 citation statements)

References 44 publications

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“…13a shows the power consumed by the FPGA implemented FOSyncRM system. For analyzing the power consumed by the controllers, we use the approximation methodology discussed in [81,89]. It confirms that larger power will be consumed by the system when the master and the slave system show largest Lyapunov exponents (FOSyn-cRM = 0.995) as shown in Fig.…”

Section: Fpga Implementation Of the Foasmcmentioning

confidence: 84%

Fractional Order Synchronous Reluctance Motor: Analysis, Chaos Control and FPGA Implementation

Rajagopal

Nazarimehr

Srinivasan³

et al. 2017

Asian Journal of Control

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This paper deals with the dynamical analysis and chaos control in a fractional order synchronous reluctance motor (FOSyncRM). Equilibrium points, characteristic equations and Eigen values of both commensurate and incommensurate FOSyncRM are presented. finite‐time Lyapunov exponents of the FOSyncRM system for fixed and varied parameters are investigated along with the bifurcation plots. Fractional order bifurcation plots are derived to show that the system shows more complex chaotic oscillations in fractional order. Chaos control in the FOSyncRM system is achieved using adaptive sliding mode controllers and the entire control algorithm is implemented in FPGA.

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Section: Fpga Implementation Of the Foasmcmentioning

confidence: 84%

Fractional Order Synchronous Reluctance Motor: Analysis, Chaos Control and FPGA Implementation

Rajagopal

Nazarimehr

Srinivasan³

et al. 2017

Asian Journal of Control

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“…e multistable modified fourth-order autonomous Chua's chaotic system presented in this study is modeled on Lab-VIEW FPGA using Runge-Kutta (RK-4) algorithm, which is one of the most popular numerical differential equation decryption methods in the literature. According to the 32-bit IEEE 754-1985 floating-point number standard, the design is coded on VHDL (Very-High-Speed High Speed Integrated Circuit Hardware Description Language) [98]. IP core generator developed by Vivado 2018.3 Design Tools system is used to design chaotic oscillator based on FPGA, such as multiplier, subtractor, and adder, which conform to IEEE 754-1985 standard.…”

Section: Fpga Implementation Of the Multistable Modified Fourth-ordermentioning

confidence: 99%

CCII and FPGA Realization: A Multistable Modified Fourth-Order Autonomous Chua’s Chaotic System with Coexisting Multiple Attractors

Shen

Liu

et al. 2020

Complexity

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In this paper, a multistable modified fourth-order autonomous Chua’s chaotic system is investigated. In addition to the dynamic characteristics of the third-order Chua’s chaotic system itself, what interests us is that this modified fourth-order autonomous Chua’s chaotic system has five different types of coexisting attractors: double-scroll, single band chaotic attractor, period-4 limit cycle, period-2 limit cycle, and period-1 limit cycle. Then, an inductorless modified fourth-order autonomous Chua’s chaotic circuit is proposed. The active elements as well as the synthetic inductor employed in this circuit are designed using second-generation current conveyors (CCIIs). The reason for using CCIIs is that they have high conversion rate and operation speed, which enable the circuit to work at a higher frequency range. The Multisim simulations confirm the theoretical estimates of the performance of the proposed circuit. Finally, using RK-4 numerical algorithm of VHDL 32-bit IQ-Math floating-point number format, the inductorless modified fourth-order autonomous Chua’s chaotic system is implemented on FPGA for the development of embedded engineering applications based on chaos. The system is simulated and synthesized on Virtex-6 FPGA chip. The maximum operating frequency of modified Chua’s chaotic oscillator based on FPGA is 180.180 MHz. This study demonstrates that the hardware-based multistable modified fourth-order autonomous Chua’s chaotic system is a very good source of entropy and can be applied to various embedded systems based on chaos, including secure communication, cryptography, and random number generator.

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“…Many literatures have discussed about the implementation of integer order systems using FPGA's [3,9,15,35,37,42,51,53]. Even though there are many literatures on the integer order FPGA implementations, less have been investigated on fractional order FPGA implementations.…”

Section: Field Programmable Gate Array (Fpga) Implementation Of Fosrcmentioning

confidence: 99%

Fractional Order Simple Chaotic Oscillator with Saturable Reactors and Its Engineering Applications

Rajagopal

Jafari

Kaçar

et al. 2019

ITC

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Chaos is often observed in forced nonlinear electrical circuits with saturable reactors. Simplest of such a circuit is presented and investigated in both integer order and non-integer (fractional) order form. For numerical analysis of fractional order system, the Adam-Bashforth-Moulton method is used. Some dynamic properties of the novel system are investigated. For implementing the system in field programmable gate arrays (FPGA), the Adomian decomposition method is used. Power and resource utilization of the fractional order system for implementing in FPGA are presented. Also, in this work, a novel fractional based sound encryption application is implemented as a unique application.

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Hyperchaotic Chameleon: Fractional Order FPGA Implementation

Cited by 53 publications

References 44 publications

Fractional Order Synchronous Reluctance Motor: Analysis, Chaos Control and FPGA Implementation

Fractional Order Synchronous Reluctance Motor: Analysis, Chaos Control and FPGA Implementation

CCII and FPGA Realization: A Multistable Modified Fourth-Order Autonomous Chua’s Chaotic System with Coexisting Multiple Attractors

Fractional Order Simple Chaotic Oscillator with Saturable Reactors and Its Engineering Applications

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