HYPER-LP: A System for Power Minimization Using Architectural Transformations

Chandrakasan, Anantha P.; Potkonjak, Miodrag; Rabaey, Jan M.; Brodersen, R.W.

doi:10.1007/978-1-4615-0292-0_10

Cited by 10 publications

(16 citation statements)

References 3 publications

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“…We therefore formulate mapping of loop l of a loop nest onto a parallel computing platform in problem (10)(11)(12)(13)(14)(15)(16)(17)(18)(19) shown in the right-hand side of Fig. 5; detailed discussion can be found in [29].…”

Section: Udt2 With Mapreduce and Pipeliningmentioning

confidence: 99%

“…For example, UDT1 transformation generates a design that utilizes C 0 f DSP blocks, increases memory bandwidth to M 0 b when introducing on-chip buffers, and achieves a system speed T 0 . When the problem (10)(11)(12)(13)(14)(15)(16)(17)(18)(19) is instantiated, M b in (11) is replaced with M 0 b and C f in the constraint (15) for DSP resource becomes C f À C 0 f . After the instantiation, the problem is solved.…”

Section: Udt2 With Mapreduce and Pipeliningmentioning

confidence: 99%

“…High-level synthesis frameworks, SPARK [14], ROCCC [15], DEFACTO [16], HYPER-LP [17], and LegUp [18], perform optimization transformations, such as code motion, loop transformation, dynamic renaming, pipelining, retiming, scalar replacement, data reuse, operation chaining, and area-saving binding, to optimize hardware circuit performance. In these frameworks, heuristic and probabilistic optimization algorithms are used to guide the transformations.…”

Section: Introductionmentioning

confidence: 99%

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Optimizing Hardware Design by Composing Utility-Directed Transformations

Liu

Todman

Luk

et al. 2012

IEEE Trans. Comput.

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Utility-directed transformations involve changing a design to optimize for given constraints while preserving behavior. These changes are often achieved by techniques such as linear programming or geometric programming. We present a systematic approach composing multiple utility-directed transformations for optimizing and mapping a sequential design onto a customizable parallel computing platform such as a Field-Programmable Gate Array (FPGA). Our aim is to enable automatic design optimization at compile time. Design goals specified by users drive the design transformations. Each utility-directed transformation achieves part of the overall goal, and multiple utility-directed transformations, connected by pattern-directed transformations, are composed to fulfill the overall design requirements. The utility-directed transformations in this work produce performance-optimized designs by exploiting data reuse, MapReduce, and pipelining for the target parallel computing platform. Moreover, it is shown that performing transformations in different orders allows users to trade speed for resources, and design performance for compile time. Several applications are used to evaluate this approach on FPGAs. The system performance of a 64-bit matrix multiplication is shown to improve up to 98 times compared to the original design, in the target hardware platform.

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Section: Udt2 With Mapreduce and Pipeliningmentioning

confidence: 99%

Section: Udt2 With Mapreduce and Pipeliningmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Optimizing Hardware Design by Composing Utility-Directed Transformations

Liu

Todman

Luk

et al. 2012

IEEE Trans. Comput.

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“…Architectural choices can impact the amount of concurrency, multiplexing, and frequency of a design, so the search problem for the best architecture is a very difficult one. Voltage reduction, combined with concurrent computation and multiplexing have been applied mainly to DSP designs [50]. Other approaches aim to construct the architecture in a way that maintains a locality of reference.…”

Section: Architectural Levelmentioning

confidence: 99%

Low-power design methodology: power estimation and optimization

Najm

Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg

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“…In 1992, Chandrakasan et al presented HyperLP [3,2], which is a tool to minimise power consumption of datapath intensive CMOS ASICs using a variety of architectural and computational transformation techniques. This tool doesn't account for the changes introduced by physical low-power processes, especially the domination of the interconnect.…”

Section: Other Approachesmentioning

confidence: 99%

A framework for low power audio design

Voß

Mertsching

17th International Conference on VLSI Design. Proceedings.

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Our goal is to develop a power-optimised technology independent macro-module library to support a fast and efficient design methodology for digital signal processing hardware. The library is embedded into a design-framework which supports an easy high-level data-flow oriented construction of signal processing algorithms using abstract function prototypes and allows an automatic optimisation and verification. The macros implement a variety of architectural and algorithmic transformations for DSP-functions as well as basic arithmetic components. Our approach differs from existing high-level low-power synthesis tools mainly in two points: Firstly, the framework embodies a psycho-acoustically motivated measurement of the output signal quality to ensure that the signal processing does not distort the signal beyond a limit while allowing transformations affecting the overall signal quality. Secondly, by defining hierarchy-levels for all modules, we can combine high level transformations for complex operations like filters with a set of basic arithmetic macros implementing various number representations and number systems like signmagnitude, two's-complement or fixed-and floating point numbers and logarithmic and residue number systems.

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HYPER-LP: A System for Power Minimization Using Architectural Transformations

Cited by 10 publications

References 3 publications

Optimizing Hardware Design by Composing Utility-Directed Transformations

Optimizing Hardware Design by Composing Utility-Directed Transformations

Low-power design methodology: power estimation and optimization

A framework for low power audio design

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